Presentation title
An Interconnect-centric Approach to Propel the Next Generation of Embedded SystemsAuthors
Davide Bertozzi and Michele FavalliInstitution(s)
University of FerraraPresentation type
Presentation of a research group from one or more scientific institutionsAbstract
The Multiprocessor System-on-Chip Research Group at University of Ferrara targets high-performance embedded computing platforms. Historically, the group made inroads into the field beginning from a core research activity on all aspects of on-chip communication. Given the fundamental system integration role played by the on-chip interconnection fabric, the research scope quickly extended both horizontally (e.g., interaction with the memory sub-system, globally-asynchronos locally-synchronous systems) and vertically (e.g., design toolflows, technology-aware decision making).
Today, while high performance and low power are still the features that embedded systems are expected to have, the emergence of new hardware and software technologies (e.g., heterogeneous multicore systems, Internet of Things, and deep learning) are posing the requirement for disruptive design solutions. In particular, the software consolidation trend causes the underlying hardware platform (a heterogeneous parallel computing architecture) to be shared among a number of concurrent applications with possibly heterogeneous performance/reliability/security requirements. At the same time, embedded systems will become increasingly analytics-driven, requiring to fuse engineering data from multiple sources and to combine them in real time with embedded control systems to automate actions and decisions.
Our approach is to view these trends as converging into highly-adaptive embedded system architectures where the allocation of processing, memory and interconnection resources to applications can be dynamically and efficiently re-modulated, thus adapting it to the application phase and to the “quality” of incoming data. We are developing an architecture supporting the “compute-just-what-you-need” paradigm coupled with fast runtime adaptivity, capable of tackling the online data analysis and reduction challenge while targeting aggressive performance-power trade-off points.
System safety and reliability are ensured with exhaustive test and verification, with emphasis on the system interconnect given its critical role as a potential source of global failures. Our approach to this issue is fundamentally cross-layer. In fact, the widening application of embedded computing systems to areas as diverse as factory automation, environmental data collection, and surveillance has brought computers into extreme environments (e.g., high/low temperature, high humidity, lightning, and radiation) that can make their components more susceptible to faults. If systems fail, we may suffer some inconvenience, even life-threatening. Enhancing the reliability of embedded systems over a widening range of different power, energy and performance working points to avoid possible harm is a challenge that the research group is actively committed to tackle.
Last but not least, the group targets more forward looking research by addressing the use of emerging interconnect technologies to propel high-end embedded systems into a new performance trajectory and impact the actual runtime performance of relevant computing tasks for power-starved embedded applications. Ultimately, the goal of this research is to demonstrate that photonic technologies can be integrated within embedded microprocessors and enable seamless, energy-efficient, high-capacity communications within and between the microprocessor and DRAM. At the same time, a relentless effort is currently underway to bring photonically-integrated architectures within reach of design automation. It is envisioned that optical interconnect technology will be especially useful for those platforms where extreme performance coupled with low size, weight, and power is a necessity (e.g. UAVs, and satellites).
Additional material
- Presentation slides: [pdf]
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