Presentation title

The importance of memory in the next generation of real-time systems

Authors

Paolo Burgio and Marko Bertogna

Institution(s)

University of Modena

Presentation type

Technical presentation

Abstract

The recent multi-core revolution triggered a series of technological challenges involving a wide spectrum of computing applications. As clock speeds cannot be further increased from last decade’s standards, the higher number of transistors made available by modern integration technologies is being exploited by integrating multiple cores on the same chip. This is opening to a series of technological challenges in the real-time and embedded computing market, ranging from the parallelization of existing applications, to the simultaneous elaboration of multiple sensor data, to the need for predictable timing guarantees of applications requiring a prompt interaction with the user/environment.

Unfortunately, itis difficult to provide predictable timing guarantees in a platform where multiple cores may contend for shared resources, the most important undoubtedly being the shared memory banks. In the OPEN-NEXT project , we intend to bridge this technological gap, selecting the most suitable and practical scheduling techniques from the recent real-time literature, and implementing them on modern embedded multi-core platforms for the embedded market. To this extent, an exhaustive exploration of the targeted computing platform is paramount to assess its potential in terms of predictable performance, and to derive worst-case analysis that can support and schedulability framework.

We will present a preliminary analysis of three cutting-edge platforms for industrial and automotive systems, namely an NXP iMX6 quad-core and two heterogeneous embedded boards, NVIDIA Tegra X1 and Xilinx Ultrascale. In this presentation, we highlight the possible source of contentions of the shared memory banks, that ultimately might harness the performance and predictability potential of the whole platform, and propose techniques to mitigate them.

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Additional material

• Extended abstract: [pdf]
• Presentation slides: [pdf]
• Full paper:

  Roberto Cavicchioli, Nicola Capodieci and Marko Bertogna.
  Memory Interference Characterization between CPU cores and integrated GPUs in Mixed-Criticality Platforms.
  22nd IEEE International Conference on Emerging Technologies And Factory Automation, Limassol, 2017.

• H2020 Project Hercules, Deliverable 2.2: Detailed characterization of platforms: [pdf]
• Open-Next Project: [web-site]

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