Presentation title

Innovation and Evolution of Hepsycode Framework: an Extended Methodology for HW/SW Co-Design of Mixed-Criticality and Real-Time Embedded Systems

Authors

Vittoriano Muttillo, Giacomo Valente and Luigi Pomante

Institution(s)

Università degli studi dell'Aquila, Italy

Presentation type

Technical presentation

Abstract

Heterogeneous parallel devices are becoming widely diffused in the embedded systems domain, mainly because of the opportunities to improve performance and, at the same time, other orthogonal metrics (e.g. cost, power and energy dissipation, area etc.). In such a context, the introduction of safety integrity levels (dictated by the standards) into embedded applications, considering shared resources on a heterogeneous parallel HW platform, adds further challenges in industrial and academic researches. This kind of (heterogeneous) multi-processor/cores (i.e. parallel) platforms that execute embedded applications with different levels of criticality are commonly called Mixed-Criticality Embedded Systems (MCESs), where the criticality of an application is an indication of the level of integrity and/or persistence required for the application itself. The main problem in the management of this MCES is to ensure that low criticality applications do not interfere with the high criticality ones. The goal is always to allow these applications to interact and coexist on the same platform, but a proper management of such mixed criticality systems becomes a very complex task that poses also several challenges from the implementation point of view. The exploitation of virtualization (i.e. Hypervisors) technologies allows to guarantee isolation and to satisfy certification requirements, but introduces scheduling overhead and new HW/SW partitioning challenges. The choice of the best hypervisors partitioning model, the number of criticality levels and the number of partitions are just some of them. In such a scenario, this presentation focuses on a framework (and related tool) for modeling, analysis and validation of mixed critical and real-time systems, through the exploitation of an existing Model-Based Electronic System Level (ESL) HW/SW Co-Design methodology (called Hepsycode: HW/SW CO-DEsign of HEterogeneous Parallel dedicated SYstems), improved to provide estimates, metrics and simulations able to consider both real-time (RT) and mixed-criticality (MC) requirements. During the last years the Hepsycode framework has been changed considerably, proposing a design flow as-much-as-possible suitable for modeling applications in different domains (i.e. automotive, aerospace, railway etc.), where applications are always characterized by the presence of tasks whose execution is critical (typically related to safety issues) and tasks whose execution is not critical, and the assignment of the criticality level is often driven by safety and security constraints compliant with certified standards. So, starting from different HW-based, OS-based, and Hypervisor-based solutions (both in the research and industrial domains), using specific modeling technologies, metrics evaluation and estimation activities, and specific HW/SW co-simulator integrated into the Hepsycode Co-Design methodology and framework, it is possible to find best sub-optimal solution for HW/SW partitioning problems by suggesting both the platform and mapping solutions, exploiting hypervisor SW partitions, schedulability analysis and final validation activities to guarantees bounded errors and solution as-much-as-possible close to the real behavioral and timing execution.

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Additional material

• Presentation slides: [pdf]

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