| Records |
Author  |
Tronci, Enrico |
| Title |
Equational Programming in lambda-calculus |
Type |
Conference Article |
| Year |
1991 |
Publication |
Sixth Annual IEEE Symposium on Logic in Computer Science (LICS) |
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Pages |
191-202 |
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IEEE Computer Society |
Place of Publication |
Amsterdam, The Netherlands |
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Approved |
yes |
| Call Number |
Sapienza @ mari @ lics91 |
Serial |
58 |
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| Author |
Tronci, Enrico |
| Title |
On Computing Optimal Controllers for Finite State Systems |
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Conference Article |
| Year |
1997 |
Publication |
CDC '97: Proceedings of the 36th IEEE International Conference on Decision and Control |
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IEEE Computer Society |
Place of Publication |
Washington, DC, USA |
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yes |
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Sapienza @ mari @ cdc97 |
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66 |
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| Author |
Tronci, Enrico |
| Title |
Optimal Finite State Supervisory Control |
Type |
Conference Article |
| Year |
1996 |
Publication |
CDC '96: Proceedings of the 35th IEEE International Conference on Decision and Control |
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Supervisory Controllers are Discrete Event Dynamic Systems (DEDSs) forming the discrete core of a Hybrid Control System. We address the problem of automatic synthesis of Optimal Finite State Supervisory Controllers (OSCs). We show that Boolean First Order Logic (BFOL) and Binary Decision Diagrams (BDDs) are an effective methodological and practical framework for Optimal Finite State Supervisory Control. Using BFOL programs (i.e. systems of boolean functional equations) and BDDs we give a symbolic (i.e. BDD based) algorithm for automatic synthesis of OSCs. Our OSC synthesis algorithm can handle arbitrary sets of final states as well as plant transition relations containing loops and uncontrollable events (e.g. failures). We report on experimental results on the use of our OSC synthesis algorithm to synthesize a C program implementing a minimum fuel OSC for two autonomous vehicles moving on a 4 x 4 grid. |
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IEEE Computer Society |
Place of Publication |
Washington, DC, USA |
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yes |
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Sapienza @ mari @ cdc96 |
Serial |
67 |
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| Author |
Tronci, Enrico; Della Penna, Giuseppe; Intrigila, Benedetto; Venturini Zilli, Marisa |
| Title |
A Probabilistic Approach to Automatic Verification of Concurrent Systems |
Type |
Conference Article |
| Year |
2001 |
Publication |
8th Asia-Pacific Software Engineering Conference (APSEC) |
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317-324 |
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The main barrier to automatic verification of concurrent systems is the huge amount of memory required to complete the verification task (state explosion). In this paper we present a probabilistic algorithm for automatic verification via model checking. Our algorithm trades space with time. In particular, when memory is full because of state explosion our algorithm does not give up verification. Instead it just proceeds at a lower speed and its results will only hold with some arbitrarily small error probability. Our preliminary experimental results show that by using our probabilistic algorithm we can typically save more than 30% of RAM with an average time penalty of about 100% w.r.t. a deterministic state space exploration with enough memory to complete the verification task. This is better than giving up the verification task because of lack of memory. |
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IEEE Computer Society |
Place of Publication |
Macau, China |
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0-7695-1408-1 |
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yes |
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Sapienza @ mari @ apsec01 |
Serial |
43 |
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| Author |
Tronci, Enrico; Della Penna, Giuseppe; Intrigila, Benedetto; Venturini Zilli, Marisa |
| Title |
Exploiting Transition Locality in Automatic Verification |
Type |
Conference Article |
| Year |
2001 |
Publication |
11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME) |
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259-274 |
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In this paper we present an algorithm to contrast state explosion when using Explicit State Space Exploration to verify protocols. We show experimentally that protocols exhibit transition locality. We present a verification algorithm that exploits transition locality as well as an implementation of it within the Mur$\varphi$ verifier. Our algorithm is compatible with all Breadth First (BF) optimization techniques present in the Mur$\varphi$ verifier and it is by no means a substitute for any of them. In fact, since our algorithm trades space with time, it is typically most useful when one runs out of memory and has already used all other state reduction techniques present in the Mur$\varphi$ verifier. Our experimental results show that using our approach we can typically save more than 40% of RAM with an average time penalty of about 50% when using (Mur$\varphi$) bit compression and 100% when using bit compression and hash compaction. |
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Springer |
Place of Publication |
Livingston, Scotland, UK |
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Margaria, T.; Melham, T.F. |
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Lecture Notes in Computer Science |
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2144 |
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3-540-42541-1 |
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yes |
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Sapienza @ mari @ charme01 |
Serial |
44 |
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| Author |
Verzino Giovanni ; Cavaliere, Federico; Mari, Federico; Melatti, Igor; Minei, Giovanni; Salvo, Ivano; Yushtein, Yuri; Tronci, Enrico |
| Title |
Model checking driven simulation of sat procedures |
Type |
Conference Article |
| Year |
2012 |
Publication |
Proceedings of 12th International Conference on Space Operations (SpaceOps 2012) |
Abbreviated Journal |
International Conference on Space Operations |
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no |
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Sapienza @ melatti @ |
Serial |
117 |
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