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Author Cavaliere, Federico; Mari, Federico; Melatti, Igor; Minei, Giovanni; Salvo, Ivano; Tronci, Enrico; Verzino, Giovanni; Yushtein, Yuri
Title Model Checking Satellite Operational Procedures Type Conference Article
Year 2011 Publication DAta Systems In Aerospace (DASIA), Org. EuroSpace, Canadian Space Agency, CNES, ESA, EUMETSAT. San Anton, Malta, EuroSpace. Abbreviated Journal
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Abstract We present a model checking approach for the automatic verification of satellite operational procedures (OPs). Building a model for a complex system as a satellite is a hard task. We overcome this obstruction by using a suitable simulator (SIMSAT) for the satellite. Our approach aims at improving OP quality assurance by automatic exhaustive exploration of all possible simulation scenarios. Moreover, our solution decreases OP verification costs by using a model checker (CMurphi) to automatically drive the simulator. We model OPs as user-executed programs observing the simulator telemetries and sending telecommands to the simulator. In order to assess feasibility of our approach we present experimental results on a simple meaningful scenario. Our results show that we can save up to 90% of verification time.
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Notes Approved yes
Call Number (down) Sapienza @ mari @ Dasia11 Serial 13
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Author Mazzini, Silvia; Puri, Stefano; Mari, Federico; Melatti, Igor; Tronci, Enrico
Title Formal Verification at System Level Type Conference Article
Year 2009 Publication In: DAta Systems In Aerospace (DASIA), Org. EuroSpace, Canadian Space Agency, CNES, ESA, EUMETSAT. Instanbul, Turkey, EuroSpace Abbreviated Journal
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Abstract System Level Analysis calls for a language comprehensible to experts with different background and yet precise enough to support meaningful analyses. SysML is emerging as an effective balance between such conflicting goals. In this paper we outline some the results obtained as for SysML based system level functional formal verification by an ESA/ESTEC study, with a collaboration among INTECS and La Sapienza University of Roma. The study focuses on SysML based system level functional requirements techniques.
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Call Number (down) Sapienza @ mari @ Dasia09 Serial 20
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Author Bobbio, Andrea; Ciancamerla, Ester; Di Blasi, Saverio; Iacomini, Alessandro; Mari, Federico; Melatti, Igor; Minichino, Michele; Scarlatti, Alessandro; Tronci, Enrico; Terruggia, Roberta; Zendri, Emilio
Title Risk analysis via heterogeneous models of SCADA interconnecting Power Grids and Telco networks Type Conference Article
Year 2009 Publication Proceedings of Fourth International Conference on Risks and Security of Internet and Systems (CRiSIS) Abbreviated Journal
Volume Issue Pages 90-97
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Abstract The automation of power grids by means of supervisory control and data acquisition (SCADA) systems has led to an improvement of power grid operations and functionalities but also to pervasive cyber interdependencies between power grids and telecommunication networks. Many power grid services are increasingly depending upon the adequate functionality of SCADA system which in turn strictly depends on the adequate functionality of its communication infrastructure. We propose to tackle the SCADA risk analysis by means of different and heterogeneous modeling techniques and software tools. We demonstrate the applicability of our approach through a case study on an actual SCADA system for an electrical power distribution grid. The modeling techniques we discuss aim at providing a probabilistic dependability analysis, followed by a worst case analysis in presence of malicious attacks and a real-time performance evaluation.
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Area Expedition Conference Fourth International Conference on Risks and Security of Internet and Systems (CRiSIS)
Notes Approved yes
Call Number (down) Sapienza @ mari @ crisis09 Serial 17
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Author Alimguzhin, Vadim; Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico
Title Automatic Control Software Synthesis for Quantized Discrete Time Hybrid Systems Type Conference Article
Year 2012 Publication Proceedings of the 51th IEEE Conference on Decision and Control, CDC 2012, December 10-13, 2012, Maui, HI, USA Abbreviated Journal
Volume Issue Pages 6120-6125
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Publisher IEEE Place of Publication Editor
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ISSN ISBN 978-1-4673-2065-8 Medium
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Notes Techreport version can be found at http://arxiv.org/abs/1207.4098 Approved yes
Call Number (down) Sapienza @ mari @ cdc12 Serial 96
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Author Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico
Title Synthesis of Quantized Feedback Control Software for Discrete Time Linear Hybrid Systems Type Conference Article
Year 2010 Publication Computer Aided Verification Abbreviated Journal
Volume Issue Pages 180-195
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Abstract We present an algorithm that given a Discrete Time Linear Hybrid System returns a correct-by-construction software implementation K for a (near time optimal) robust quantized feedback controller for along with the set of states on which K is guaranteed to work correctly (controllable region). Furthermore, K has a Worst Case Execution Time linear in the number of bits of the quantization schema.
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Publisher Springer Berlin / Heidelberg Place of Publication Editor Touili, T.; Cook, B.; Jackson, P.
Language Summary Language Original Title
Series Editor Series Title Lecture Notes in Computer Science Abbreviated Series Title
Series Volume 6174 Series Issue Edition
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Area Expedition Conference
Notes Approved yes
Call Number (down) Sapienza @ mari @ cav2010 Serial 16
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Author Brizzolari, Francesco; Melatti, Igor; Tronci, Enrico; Della Penna, Giuseppe
Title Disk Based Software Verification via Bounded Model Checking Type Conference Article
Year 2007 Publication APSEC '07: Proceedings of the 14th Asia-Pacific Software Engineering Conference Abbreviated Journal
Volume Issue Pages 358-365
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Abstract One of the most successful approach to automatic software verification is SAT based bounded model checking (BMC). One of the main factors limiting the size of programs that can be automatically verified via BMC is the huge number of clauses that the backend SAT solver has to process. In fact, because of this, the SAT solver may easily run out of RAM. We present two disk based algorithms that can considerably decrease the number of clauses that a BMC backend SAT solver has to process in RAM. Our experimental results show that using our disk based algorithms we can automatically verify programs that are out of reach for RAM based BMC.
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Publisher IEEE Computer Society Place of Publication Washington, DC, USA Editor
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Series Volume Series Issue Edition
ISSN 0-7695-3057-5 ISBN Medium
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Notes Approved yes
Call Number (down) Sapienza @ mari @ Bmtd07 Serial 76
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Author Mancini, T. ; Mari, F.; Massini, A.; Melatti, I.; Salvo, I.; Tronci, E.
Title On minimising the maximum expected verification time Type Journal Article
Year 2017 Publication Information Processing Letters Abbreviated Journal
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Notes Approved no
Call Number (down) Sapienza @ mari @ Serial 163
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Author Tronci, E.; Mancini, T.; Salvo, I.; Mari, F.; Melatti, I.; Massini, A.; Sinisi, S.; Davì, F.; Dierkes, T.; Ehrig, R.; Röblitz, S.; Leeners, B.; Krüger, T.; Egli, M.; Ille, F.
Title Patient-Specific Models from Inter-Patient Biological Models and Clinical Records Type Conference Article
Year 2014 Publication Formal Methods in Computer-Aided Design (FMCAD) Abbreviated Journal
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Notes Approved no
Call Number (down) Sapienza @ mari @ Serial 120
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Author Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico
Title Model Based Synthesis of Control Software from System Level Formal Specifications Type Report
Year 2013 Publication Abbreviated Journal
Volume abs/1107.5638 Issue Pages
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Abstract Many Embedded Systems are indeed Software Based Control Systems, that is control systems whose controller consists of control software running on a microcontroller device. This motivates investigation on Formal Model Based Design approaches for automatic synthesis of embedded systems control software.
We present an algorithm, along with a tool QKS implementing it, that from a formal model (as a Discrete Time Linear Hybrid System) of the controlled system (plant), implementation specifications (that is, number of bits in the Analog-to-Digital, AD, conversion) and System Level Formal Specifications (that is, safety and liveness requirements for the closed loop system) returns correct-by-construction control software that has a Worst Case Execution Time (WCET) linear in the number of AD bits and meets the given specifications.
We show feasibility of our approach by presenting experimental results on using it to synthesize control software for a buck DC-DC converter, a widely used mixed-mode analog circuit, and for the inverted pendulum.
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Publisher CoRR, Technical Report Place of Publication Editor
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Notes Approved yes
Call Number (down) Sapienza @ mari @ Serial 104
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Author Mancini, Toni; Mari, Federico; Massini, Annalisa; Melatti, Igor; Merli, Fabio; Tronci, Enrico
Title System Level Formal Verification via Model Checking Driven Simulation Type Conference Article
Year 2013 Publication Proceedings of the 25th International Conference on Computer Aided Verification. July 13-19, 2013, Saint Petersburg, Russia Abbreviated Journal CAV 2013
Volume Issue Pages 296-312
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Publisher Springer - Verlag Place of Publication Editor
Language Summary Language Original Title
Series Editor Series Title Lecture Notes in Computer Science Abbreviated Series Title
Series Volume 8044 Series Issue Edition
ISSN 0302-9743 ISBN 978-3-642-39798-1 Medium
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Notes Approved yes
Call Number (down) Sapienza @ mari @ Serial 113
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