| Records |
| Author |
Mancini, T.; Mari, F.; Melatti, I.; Salvo, I.; Tronci, E.; Gruber, J.K.; Hayes, B.; Prodanovic, M.; Elmegaard, L. |
| Title |
User Flexibility Aware Price Policy Synthesis for Smart Grids |
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Conference Article |
| Year |
2015 |
Publication |
Digital System Design (DSD), 2015 Euromicro Conference on |
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478-485 |
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Contracts; Current measurement; Load management; Power demand; Power measurement; State estimation; Substations; Grid State Estimation; Peak Shaving; Policy Robustness Verification; Price Policy Synthesis |
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Sapienza @ preissler @ Mancini_etal2015_3 |
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136 |
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| Author |
Mancini, T.; Mari, F.; Melatti, I.; Salvo, I.; Tronci, E. |
| Title |
An Efficient Algorithm for Network Vulnerability Analysis Under Malicious Attacks |
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Conference Article |
| Year |
2018 |
Publication |
Foundations of Intelligent Systems – 24th International Symposium, ISMIS 2018, Limassol, Cyprus, October 29-31, 2018, Proceedings |
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302-312 |
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Best Paper |
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no |
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MCLab @ davi @ DBLP:conf/ismis/ManciniMMST18 |
Serial |
176 |
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Mancini, T.; Mari, F.; Massini, A.; Melatti, I.; Tronci, E. |
| Title |
Anytime system level verification via parallel random exhaustive hardware in the loop simulation |
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Journal Article |
| Year |
2016 |
Publication |
Microprocessors and Microsystems |
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| Volume |
41 |
Issue |
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Pages |
12-28 |
| Keywords |
Model Checking of Hybrid Systems; Model checking driven simulation; Hardware in the loop simulation |
| Abstract |
Abstract System level verification of cyber-physical systems has the goal of verifying that the whole (i.e., software + hardware) system meets the given specifications. Model checkers for hybrid systems cannot handle system level verification of actual systems. Thus, Hardware In the Loop Simulation (HILS) is currently the main workhorse for system level verification. By using model checking driven exhaustive HILS, System Level Formal Verification (SLFV) can be effectively carried out for actual systems. We present a parallel random exhaustive HILS based model checker for hybrid systems that, by simulating all operational scenarios exactly once in a uniform random order, is able to provide, at any time during the verification process, an upper bound to the probability that the System Under Verification exhibits an error in a yet-to-be-simulated scenario (Omission Probability). We show effectiveness of the proposed approach by presenting experimental results on SLFV of the Inverted Pendulum on a Cart and the Fuel Control System examples in the Simulink distribution. To the best of our knowledge, no previously published model checker can exhaustively verify hybrid systems of such a size and provide at any time an upper bound to the Omission Probability. |
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0141-9331 |
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no |
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MCLab @ davi @ Mancini201612 |
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155 |
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Alimguzhin, V.; Mari, F.; Melatti, I.; Tronci, E.; Ebeid, E.; Mikkelsen, S.A.; Jacobsen, R.H.; Gruber, J.K.; Hayes, B.; Huerta, F.; Prodanovic, M. |
| Title |
A Glimpse of SmartHG Project Test-bed and Communication Infrastructure |
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Conference Article |
| Year |
2015 |
Publication |
Digital System Design (DSD), 2015 Euromicro Conference on |
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Issue |
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225-232 |
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Batteries; Control systems; Databases; Production; Sensors; Servers; Smart grids; Grid State Estimation; Peak Shaving; Policy Robustness Verification; Price Policy Synthesis |
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no |
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Sapienza @ preissler @ Alimguzhin_etal2015 |
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127 |
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Mancini, Toni; Mari, Federico; Massini, Annalisa; Melatti, Igor; Tronci, Enrico |
| Title |
Simulator Semantics for System Level Formal Verification |
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Conference Article |
| Year |
2015 |
Publication |
Proceedings Sixth International Symposium on Games, Automata, Logics and Formal Verification (GandALF 2015), |
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no |
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MCLab @ davi @ |
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125 |
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Toni Mancini; Enrico Tronci; Ivano Salvo; Federico Mari; Annalisa Massini; Igor Melatti |
| Title |
Computing Biological Model Parameters by Parallel Statistical Model Checking |
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Journal Article |
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2015 |
Publication |
International Work Conference on Bioinformatics and Biomedical Engineering (IWBBIO 2015) |
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9044 |
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542-554 |
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MCLab @ davi @ |
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124 |
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Della Penna, Giuseppe; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico; Venturini Zilli, Marisa |
| Title |
Finite Horizon Analysis of Markov Chains with the Mur$\varphi$ Verifier |
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Conference Article |
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2003 |
Publication |
Correct Hardware Design and Verification Methods, 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings |
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394-409 |
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In this paper we present an explicit disk based verification algorithm for Probabilistic Systems defining discrete time/finite state Markov Chains. Given a Markov Chain and an integer k (horizon), our algorithm checks whether the probability of reaching an error state in at most k steps is below a given threshold. We present an implementation of our algorithm within a suitable extension of the Mur$\varphi$ verifier. We call the resulting probabilistic model checker FHP-Mur$\varphi$ (Finite Horizon Probabilistic Mur$\varphi$). We present experimental results comparing FHP-Mur$\varphi$ with (a finite horizon subset of) PRISM, a state-of-the-art symbolic model checker for Markov Chains. Our experimental results show that FHP-Mur$\varphi$ can handle systems that are out of reach for PRISM, namely those involving arithmetic operations on the state variables (e.g. hybrid systems). |
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Springer |
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Geist, D.; Tronci, E. |
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Lecture Notes in Computer Science |
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2860 |
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3-540-20363-X |
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yes |
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Sapienza @ mari @ Dimtz03 |
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84 |
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Della Penna, Giuseppe; Tofani, Alberto; Pecorari, Marcello; Raparelli, Orazio; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico |
| Title |
A Case Study on Automated Generation of Integration Tests |
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Conference Article |
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2006 |
Publication |
Fdl |
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278-284 |
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Ecsi |
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978-3-00-019710-9 |
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yes |
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Sapienza @ mari @ Dtprimt06 |
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27 |
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Cavaliere, Federico; Mari, Federico; Melatti, Igor; Minei, Giovanni; Salvo, Ivano; Tronci, Enrico; Verzino, Giovanni; Yushtein, Yuri |
| Title |
Model Checking Satellite Operational Procedures |
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Conference Article |
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2011 |
Publication |
DAta Systems In Aerospace (DASIA), Org. EuroSpace, Canadian Space Agency, CNES, ESA, EUMETSAT. San Anton, Malta, EuroSpace. |
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We present a model checking approach for the automatic verification of satellite operational procedures (OPs). Building a model for a complex system as a satellite is a hard task. We overcome this obstruction by using a suitable simulator (SIMSAT) for the satellite. Our approach aims at improving OP quality assurance by automatic exhaustive exploration of all possible simulation scenarios. Moreover, our solution decreases OP verification costs by using a model checker (CMurphi) to automatically drive the simulator. We model OPs as user-executed programs observing the simulator telemetries and sending telecommands to the simulator. In order to assess feasibility of our approach we present experimental results on a simple meaningful scenario. Our results show that we can save up to 90% of verification time. |
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yes |
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Sapienza @ mari @ Dasia11 |
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13 |
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Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
| Title |
From Boolean Relations to Control Software |
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Conference Article |
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2011 |
Publication |
Proceedings of ICSEA 2011, The Sixth International Conference on Software Engineering Advances |
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528-533 |
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Many software as well digital hardware automatic synthesis methods define the set of implementations meeting the given system specifications with a boolean relation K. In such a context a fundamental step in the software (hardware) synthesis process is finding effective solutions to the functional equation defined by K. This entails finding a (set of) boolean function(s) F (typically represented using OBDDs, Ordered Binary Decision Diagrams) such that: 1) for all x for which K is satisfiable, K(x, F(x)) = 1 holds; 2) the implementation of F is efficient with respect to given implementation parameters such as code size or execution time. While this problem has been widely studied in digital hardware synthesis, little has been done in a software synthesis context. Unfortunately the approaches developed for hardware synthesis cannot be directly used in a software context. This motivates investigation of effective methods to solve the above problem when F has to be implemented with software. In this paper we present an algorithm that, from an OBDD representation for K, generates a C code implementation for F that has the same size as the OBDD for F and a WCET (Worst Case Execution Time) linear in nr, being n = |x| the number of input arguments for functions in F and r the number of functions in F. |
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ThinkMind |
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978-1-61208-165-6 |
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Best Paper Award |
Approved |
yes |
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Sapienza @ mari @ icsea11 |
Serial |
14 |
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