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Toni Mancini; Enrico Tronci; Ivano Salvo; Federico Mari; Annalisa Massini; Igor Melatti |
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Computing Biological Model Parameters by Parallel Statistical Model Checking |
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2015 |
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International Work Conference on Bioinformatics and Biomedical Engineering (IWBBIO 2015) |
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9044 |
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542-554 |
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MCLab @ davi @ |
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124 |
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Mancini, Toni; Mari, Federico; Massini, Annalisa; Melatti, Igor; Tronci, Enrico |
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SyLVaaS: System Level Formal Verification as a Service |
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Conference Article |
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2015 |
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Proceedings of the 23rd Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP 2015), special session on Formal Approaches to Parallel and Distributed Systems (4PAD) |
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MCLab @ davi @ |
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123 |
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Mancini, Toni; Mari, Federico; Massini, Annalisa; Melatti, Igor; Tronci, Enrico |
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Title |
Anytime System Level Verification via Random Exhaustive Hardware In The Loop Simulation |
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Conference Article |
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2014 |
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In Proceedings of 17th EuroMicro Conference on Digital System Design (DSD 2014) |
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MCLab @ davi @ |
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122 |
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Tronci, E.; Mancini, T.; Mari, F.; Melatti, I.; Salvo, I.; Prodanovic, M.; Gruber, J. K.; Hayes, B.; Elmegaard, L. |
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Demand-Aware Price Policy Synthesis and Verification Services for Smart Grids |
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2014 |
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Proceedings of Smart Grid Communications (SmartGridComm), 2014 IEEE International Conference On |
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Sapienza @ melatti @ |
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121 |
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Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Title |
Model Based Synthesis of Control Software from System Level Formal Specifications |
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Report |
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2013 |
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abs/1107.5638 |
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Many Embedded Systems are indeed Software Based Control Systems, that is control systems whose controller consists of control software running on a microcontroller device. This motivates investigation on Formal Model Based Design approaches for automatic synthesis of embedded systems control software.
We present an algorithm, along with a tool QKS implementing it, that from a formal model (as a Discrete Time Linear Hybrid System) of the controlled system (plant), implementation specifications (that is, number of bits in the Analog-to-Digital, AD, conversion) and System Level Formal Specifications (that is, safety and liveness requirements for the closed loop system) returns correct-by-construction control software that has a Worst Case Execution Time (WCET) linear in the number of AD bits and meets the given specifications.
We show feasibility of our approach by presenting experimental results on using it to synthesize control software for a buck DC-DC converter, a widely used mixed-mode analog circuit, and for the inverted pendulum. |
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CoRR, Technical Report |
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yes |
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Sapienza @ mari @ |
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104 |
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Melatti, Igor; Palmer, Robert; Sawaya, Geoffrey; Yang, Yu; Kirby, Robert Mike; Gopalakrishnan, Ganesh |
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Title |
Parallel and Distributed Model Checking in Eddy |
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2006 |
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Model Checking Software, 13th International SPIN Workshop, Vienna, Austria, March 30 – April 1, 2006, Proceedings |
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108-125 |
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Model checking of safety properties can be scaled up by pooling the CPU and memory resources of multiple computers. As compute clusters containing 100s of nodes, with each node realized using multi-core (e.g., 2) CPUs will be widespread, a model checker based on the parallel (shared memory) and distributed (message passing) paradigms will more efficiently use the hardware resources. Such a model checker can be designed by having each node employ two shared memory threads that run on the (typically) two CPUs of a node, with one thread responsible for state generation, and the other for efficient communication, including (i) performing overlapped asynchronous message passing, and (ii) aggregating the states to be sent into larger chunks in order to improve communication network utilization. We present the design details of such a novel model checking architecture called Eddy. We describe the design rationale, details of how the threads interact and yield control, exchange messages, as well as detect termination. We have realized an instance of this architecture for the Murphi modeling language. Called Eddy_Murphi, we report its performance over the number of nodes as well as communication parameters such as those controlling state aggregation. Nearly linear reduction of compute time with increasing number of nodes is observed. Our thread task partition is done in such a way that it is modular, easy to port across different modeling languages, and easy to tune across a variety of platforms. |
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Springer - Verlag |
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Valmari, A. |
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Lecture Notes in Computer Science |
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3925 |
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0302-9743 |
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978-3-540-33102-5 |
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yes |
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Sapienza @ mari @ Mpsykg06 |
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81 |
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Della Penna, Giuseppe; Tofani, Alberto; Pecorari, Marcello; Raparelli, Orazio; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico |
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A Case Study on Automated Generation of Integration Tests |
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Conference Article |
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2006 |
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Fdl |
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278-284 |
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978-3-00-019710-9 |
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Sapienza @ mari @ Dtprimt06 |
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27 |
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Cavaliere, Federico; Mari, Federico; Melatti, Igor; Minei, Giovanni; Salvo, Ivano; Tronci, Enrico; Verzino, Giovanni; Yushtein, Yuri |
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Model Checking Satellite Operational Procedures |
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2011 |
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DAta Systems In Aerospace (DASIA), Org. EuroSpace, Canadian Space Agency, CNES, ESA, EUMETSAT. San Anton, Malta, EuroSpace. |
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We present a model checking approach for the automatic verification of satellite operational procedures (OPs). Building a model for a complex system as a satellite is a hard task. We overcome this obstruction by using a suitable simulator (SIMSAT) for the satellite. Our approach aims at improving OP quality assurance by automatic exhaustive exploration of all possible simulation scenarios. Moreover, our solution decreases OP verification costs by using a model checker (CMurphi) to automatically drive the simulator. We model OPs as user-executed programs observing the simulator telemetries and sending telecommands to the simulator. In order to assess feasibility of our approach we present experimental results on a simple meaningful scenario. Our results show that we can save up to 90% of verification time. |
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Sapienza @ mari @ Dasia11 |
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13 |
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Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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From Boolean Relations to Control Software |
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2011 |
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Proceedings of ICSEA 2011, The Sixth International Conference on Software Engineering Advances |
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528-533 |
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Many software as well digital hardware automatic synthesis methods define the set of implementations meeting the given system specifications with a boolean relation K. In such a context a fundamental step in the software (hardware) synthesis process is finding effective solutions to the functional equation defined by K. This entails finding a (set of) boolean function(s) F (typically represented using OBDDs, Ordered Binary Decision Diagrams) such that: 1) for all x for which K is satisfiable, K(x, F(x)) = 1 holds; 2) the implementation of F is efficient with respect to given implementation parameters such as code size or execution time. While this problem has been widely studied in digital hardware synthesis, little has been done in a software synthesis context. Unfortunately the approaches developed for hardware synthesis cannot be directly used in a software context. This motivates investigation of effective methods to solve the above problem when F has to be implemented with software. In this paper we present an algorithm that, from an OBDD representation for K, generates a C code implementation for F that has the same size as the OBDD for F and a WCET (Worst Case Execution Time) linear in nr, being n = |x| the number of input arguments for functions in F and r the number of functions in F. |
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ThinkMind |
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978-1-61208-165-6 |
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Best Paper Award |
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Sapienza @ mari @ icsea11 |
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14 |
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Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Title |
Synthesis of Quantized Feedback Control Software for Discrete Time Linear Hybrid Systems |
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2010 |
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Computer Aided Verification |
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180-195 |
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We present an algorithm that given a Discrete Time Linear Hybrid System returns a correct-by-construction software implementation K for a (near time optimal) robust quantized feedback controller for along with the set of states on which K is guaranteed to work correctly (controllable region). Furthermore, K has a Worst Case Execution Time linear in the number of bits of the quantization schema. |
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Springer Berlin / Heidelberg |
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Touili, T.; Cook, B.; Jackson, P. |
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Lecture Notes in Computer Science |
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6174 |
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Sapienza @ mari @ cav2010 |
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16 |
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