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Author |
Chen, Q.M.; Finzi, A.; Mancini, T.; Melatti, I.; Tronci, E. |
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Title |
MILP, Pseudo-Boolean, and OMT Solvers for Optimal Fault-Tolerant Placements of Relay Nodes in Mission Critical Wireless Networks |
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Journal Article |
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Year |
2020 |
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Abbreviated Journal |
Fundamenta Informaticae |
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Volume |
174 |
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Pages |
229-258 |
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In critical infrastructures like airports, much care has to be devoted in protecting radio communication networks from external electromagnetic interference. Protection of such mission-critical radio communication networks is usually tackled by exploiting radiogoniometers: at least three suitably deployed radiogoniometers, and a gateway gathering information from them, permit to monitor and localise sources of electromagnetic emissions that are not supposed to be present in the monitored area. Typically, radiogoniometers are connected to the gateway through relay nodes . As a result, some degree of fault-tolerance for the network of relay nodes is essential in order to offer a reliable monitoring. On the other hand, deployment of relay nodes is typically quite expensive. As a result, we have two conflicting requirements: minimise costs while guaranteeing a given fault-tolerance. In this paper, we address the problem of computing a deployment for relay nodes that minimises the overall cost while at the same time guaranteeing proper working of the network even when some of the relay nodes (up to a given maximum number) become faulty (fault-tolerance ). We show that, by means of a computation-intensive pre-processing on a HPC infrastructure, the above optimisation problem can be encoded as a 0/1 Linear Program, becoming suitable to be approached with standard Artificial Intelligence reasoners like MILP, PB-SAT, and SMT/OMT solvers. Our problem formulation enables us to present experimental results comparing the performance of these three solving technologies on a real case study of a relay node network deployment in areas of the Leonardo da Vinci Airport in Rome, Italy. |
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IOS Press |
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1875-8681 |
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MCLab @ davi @ |
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188 |
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Author |
Driouich, Y.; Parente, M.; Tronci, E. |
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Title |
Model Checking Cyber-Physical Energy Systems |
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Conference Article |
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2018 |
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Proceedings of 2017 International Renewable and Sustainable Energy Conference, IRSEC 2017 |
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Institute of Electrical and Electronics Engineers Inc. |
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MCLab @ davi @ Driouich2018 |
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177 |
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Author |
Della Penna, Giuseppe; Magazzeni, Daniele; Tofani, Alberto; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico |
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Title |
Automated Generation of Optimal Controllers through Model Checking Techniques |
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Conference Article |
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Year |
2006 |
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Icinco-Icso |
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26-33 |
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We present a methodology for the synthesis of controllers, which exploits (explicit) model checking techniques. That is, we can cope with the systematic exploration of a very large state space. This methodology can be applied to systems where other approaches fail. In particular, we can consider systems with an highly non-linear dynamics and lacking a uniform mathematical description (model). We can also consider situations where the required control action cannot be specified as a local action, and rather a kind of planning is required. Our methodology individuates first a raw optimal controller, then extends it to obtain a more robust one. A case study is presented which considers the well known truck-trailer obstacle avoidance parking problem, in a parking lot with obstacles on it. The complex non-linear dynamics of the truck-trailer system, within the presence of obstacles, makes the parking problem extremely hard. We show how, by our methodology, we can obtain optimal controllers with different degrees of robustness. |
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INSTICC Press |
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Andrade-Cetto, J.; Ferrier, J.-L.; Pereira, J. M. C. D.; Filipe, J. |
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972-8865-59-7 |
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yes |
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Sapienza @ mari @ Dimmtt06 |
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79 |
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Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico; Alvisi, Lorenzo; Clement, Allen; Li, Harry |
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Title |
Model Checking Nash Equilibria in MAD Distributed Systems |
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Conference Article |
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2008 |
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FMCAD '08: Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design |
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1-8 |
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Model Checking, MAD Distributed System, Nash Equilibrium |
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We present a symbolic model checking algorithm for verification of Nash equilibria in finite state mechanisms modeling Multiple Administrative Domains (MAD) distributed systems. Given a finite state mechanism, a proposed protocol for each agent and an indifference threshold for rewards, our model checker returns PASS if the proposed protocol is a Nash equilibrium (up to the given indifference threshold) for the given mechanism, FAIL otherwise. We implemented our model checking algorithm inside the NuSMV model checker and present experimental results showing its effectiveness for moderate size mechanisms. For example, we can handle mechanisms which corresponding normal form games would have more than $10^20$ entries. To the best of our knowledge, no model checking algorithm for verification of mechanism Nash equilibria has been previously published. |
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IEEE Press |
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Piscataway, NJ, USA |
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Cimatti, A.; Jones, R. |
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978-1-4244-2735-2 |
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yes |
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Call Number |
Sapienza @ mari @ MarMelSalTroAlvCle08 |
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93 |
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Author |
Cecconi, Michele; Tronci, Enrico |
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Title |
Requirements Formalization and Validation for a Telecommunication Equipment Protection Switcher |
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Conference Article |
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2000 |
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Hase |
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IEEE Computer Society |
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0-7695-0927-4 |
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yes |
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Call Number |
Sapienza @ mari @ CeTro00 |
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29 |
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Author |
Tronci, Enrico; Della Penna, Giuseppe; Intrigila, Benedetto; Venturini Zilli, Marisa |
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Title |
A Probabilistic Approach to Automatic Verification of Concurrent Systems |
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Conference Article |
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2001 |
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8th Asia-Pacific Software Engineering Conference (APSEC) |
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317-324 |
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The main barrier to automatic verification of concurrent systems is the huge amount of memory required to complete the verification task (state explosion). In this paper we present a probabilistic algorithm for automatic verification via model checking. Our algorithm trades space with time. In particular, when memory is full because of state explosion our algorithm does not give up verification. Instead it just proceeds at a lower speed and its results will only hold with some arbitrarily small error probability. Our preliminary experimental results show that by using our probabilistic algorithm we can typically save more than 30% of RAM with an average time penalty of about 100% w.r.t. a deterministic state space exploration with enough memory to complete the verification task. This is better than giving up the verification task because of lack of memory. |
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IEEE Computer Society |
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Macau, China |
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0-7695-1408-1 |
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yes |
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Call Number |
Sapienza @ mari @ apsec01 |
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43 |
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Author |
Dipoppa, G.; D'Alessandro, G.; Semprini, R.; Tronci, E. |
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Title |
Integrating Automatic Verification of Safety Requirements in Railway Interlocking System Design |
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Conference Article |
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2001 |
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High Assurance Systems Engineering, 2001. Sixth IEEE International Symposium on |
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209-219 |
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A railway interlocking system (RIS) is an embedded system (namely a supervisory control system) that ensures the safe, operation of the devices in a railway station. RIS is a safety critical system. We explore the possibility of integrating automatic formal verification methods in a given industry RIS design flow. The main obstructions to be overcome in our work are: selecting a formal verification tool that is efficient enough to solve the verification problems at hand; and devising a cost effective integration strategy for such tool. We were able to devise a successful integration strategy meeting the above constraints without requiring major modification in the pre-existent design flow nor retraining of personnel. We run verification experiments for a RIS designed for the Singapore Subway. The experiments show that the RIS design flow obtained from our integration strategy is able to automatically verify real life RIS designs. |
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IEEE Computer Society |
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Albuquerque, NM, USA |
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0-7695-1275-5 |
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yes |
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Sapienza @ mari @ hase01 |
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45 |
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Author |
Tronci, Enrico |
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Title |
Formally Modeling a Metal Processing Plant and its Closed Loop Specifications |
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Conference Article |
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Year |
1999 |
Publication |
4th IEEE International Symposium on High-Assurance Systems Engineering (HASE) |
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151 |
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We present a case study on automatic synthesis of control software from formal specifications for an industrial automation control system. Our aim is to compare the effectiveness (i.e. design effort and controller quality) of automatic controller synthesis from closed loop formal specifications with that of manual controller design followed by automatic verification. The system to be controlled (plant) models a metal processing facility near Karlsruhe. We succeeded in automatically generating C code implementing a (correct by construction) embedded controller for such a plant from closed loop formal specifications. Our experimental results show that for industrial automation control systems automatic synthesis is a viable and profitable (especially as far as design effort is concerned) alternative to manual design followed by automatic verification. |
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IEEE Computer Society |
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Washington, D.C, USA |
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0-7695-0418-3 |
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yes |
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Sapienza @ mari @ hase99 |
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50 |
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Author |
Tronci, Enrico |
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Title |
Hardware Verification, Boolean Logic Programming, Boolean Functional Programming |
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Conference Article |
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1995 |
Publication |
Tenth Annual IEEE Symposium on Logic in Computer Science (LICS) |
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408-418 |
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One of the main obstacles to automatic verification of finite state systems (FSSs) is state explosion. In this respect automatic verification of an FSS M using model checking and binary decision diagrams (BDDs) has an intrinsic limitation: no automatic global optimization of the verification task is possible until a BDD representation for M is generated. This is because systems and specifications are defined using different languages. To perform global optimization before generating a BDD representation for M we propose to use the same language to define systems and specifications. We show that first order logic on a Boolean domain yields an efficient functional programming language that can be used to represent, specify and automatically verify FSSs, e.g. on a SUN Sparc Station 2 we were able to automatically verify a 64 bit commercial multiplier. |
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IEEE Computer Society |
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San Diego, California |
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yes |
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Sapienza @ mari @ lics95 |
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56 |
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Author |
Tronci, Enrico |
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Title |
Equational Programming in lambda-calculus |
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Conference Article |
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1991 |
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Sixth Annual IEEE Symposium on Logic in Computer Science (LICS) |
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191-202 |
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IEEE Computer Society |
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Amsterdam, The Netherlands |
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yes |
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Sapienza @ mari @ lics91 |
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58 |
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