| Records |
| Author |
Mancini, Toni; Mari, Federico; Massini, Annalisa; Melatti, Igor; Tronci, Enrico |
| Title |
Anytime System Level Verification via Random Exhaustive Hardware In The Loop Simulation |
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Conference Article |
| Year |
2014 |
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In Proceedings of 17th EuroMicro Conference on Digital System Design (DSD 2014) |
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no |
| Call Number |
MCLab @ davi @ |
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122 |
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Tronci, E.; Mancini, T.; Mari, F.; Melatti, I.; Salvo, I.; Prodanovic, M.; Gruber, J. K.; Hayes, B.; Elmegaard, L. |
| Title |
Demand-Aware Price Policy Synthesis and Verification Services for Smart Grids |
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Conference Article |
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2014 |
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Proceedings of Smart Grid Communications (SmartGridComm), 2014 IEEE International Conference On |
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no |
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Sapienza @ melatti @ |
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121 |
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Tronci, E.; Mancini, T.; Salvo, I.; Mari, F.; Melatti, I.; Massini, A.; Sinisi, S.; Davì, F.; Dierkes, T.; Ehrig, R.; Röblitz, S.; Leeners, B.; Krüger, T.; Egli, M.; Ille, F. |
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Patient-Specific Models from Inter-Patient Biological Models and Clinical Records |
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Conference Article |
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2014 |
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Formal Methods in Computer-Aided Design (FMCAD) |
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Sapienza @ mari @ |
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120 |
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Tronci, E.; Mancini, T.; Mari, F.; Melatti, I.; Jacobsen, R. H.; Ebeid, E.; Mikkelsen, S. A.; Prodanovic, M.; Gruber, J. K.; Hayes, B. |
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SmartHG: Energy Demand Aware Open Services for Smart Grid Intelligent Automation |
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Conference Article |
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2014 |
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Proceedings of the Work in Progress Session of SEAA/DSD 2014 |
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978-3-902457-40-0 |
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no |
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Sapienza @ mari @ |
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119 |
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Bobbio, Andrea; Ciancamerla, Ester; Di Blasi, Saverio; Iacomini, Alessandro; Mari, Federico; Melatti, Igor; Minichino, Michele; Scarlatti, Alessandro; Tronci, Enrico; Terruggia, Roberta; Zendri, Emilio |
| Title |
Risk analysis via heterogeneous models of SCADA interconnecting Power Grids and Telco networks |
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Conference Article |
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2009 |
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Proceedings of Fourth International Conference on Risks and Security of Internet and Systems (CRiSIS) |
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90-97 |
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The automation of power grids by means of supervisory control and data acquisition (SCADA) systems has led to an improvement of power grid operations and functionalities but also to pervasive cyber interdependencies between power grids and telecommunication networks. Many power grid services are increasingly depending upon the adequate functionality of SCADA system which in turn strictly depends on the adequate functionality of its communication infrastructure. We propose to tackle the SCADA risk analysis by means of different and heterogeneous modeling techniques and software tools. We demonstrate the applicability of our approach through a case study on an actual SCADA system for an electrical power distribution grid. The modeling techniques we discuss aim at providing a probabilistic dependability analysis, followed by a worst case analysis in presence of malicious attacks and a real-time performance evaluation. |
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Fourth International Conference on Risks and Security of Internet and Systems (CRiSIS) |
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yes |
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Sapienza @ mari @ crisis09 |
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17 |
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Verzino Giovanni ; Cavaliere, Federico; Mari, Federico; Melatti, Igor; Minei, Giovanni; Salvo, Ivano; Yushtein, Yuri; Tronci, Enrico |
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Model checking driven simulation of sat procedures |
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Conference Article |
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2012 |
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Proceedings of 12th International Conference on Space Operations (SpaceOps 2012) |
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International Conference on Space Operations |
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no |
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Sapienza @ melatti @ |
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117 |
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Mazzini, Silvia; Puri, Stefano; Mari, Federico; Melatti, Igor; Tronci, Enrico |
| Title |
Formal Verification at System Level |
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Conference Article |
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2009 |
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In: DAta Systems In Aerospace (DASIA), Org. EuroSpace, Canadian Space Agency, CNES, ESA, EUMETSAT. Instanbul, Turkey, EuroSpace |
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System Level Analysis calls for a language comprehensible to experts with different background and yet precise enough to support meaningful analyses. SysML is emerging as an effective balance between such conflicting goals. In this paper we outline some the results obtained as for SysML based system level functional formal verification by an ESA/ESTEC study, with a collaboration among INTECS and La Sapienza University of Roma. The study focuses on SysML based system level functional requirements techniques. |
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yes |
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Sapienza @ mari @ Dasia09 |
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20 |
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Alimguzhin, V.; Mari, F.; Melatti, I.; Salvo, I.; Tronci, E. |
| Title |
Linearising Discrete Time Hybrid Systems |
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2017 |
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IEEE Transactions on Automatic Control |
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62 |
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10 |
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5357-5364 |
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Model Based Design approaches for embedded systems aim at generating correct-by-construction control software, guaranteeing that the closed loop system (controller and plant) meets given system level formal specifications. This technical note addresses control synthesis for safety and reachability properties of possibly non-linear discrete time hybrid systems. By means of syntactical transformations that require non-linear terms to be Lipschitz continuous functions, we over-approximate non-linear dynamics with a linear system whose controllers are guaranteed to be controllers of the original system. We evaluate performance of our approach on meaningful control synthesis benchmarks, also comparing it to a state-of-the-art tool. |
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0018-9286 |
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no |
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Sapienza @ mari @ ref7902199 |
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164 |
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Kuijpers, Ed; Carotenuto, Luigi; Malapert, Jean-Cristophe; Markov-Vetter, Daniela; Melatti, Igor; Orlandini, Andrea; Pinchuk, Ranni |
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Collaboration on ISS Experiment Data and Knowledge Representation |
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2012 |
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Proc. of IAC 2012 |
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D.5.11 |
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yes |
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Sapienza @ melatti @ |
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107 |
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Della Penna, Giuseppe; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico; Venturini Zilli, Marisa |
| Title |
Exploiting Transition Locality in Automatic Verification of Finite State Concurrent Systems |
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2004 |
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Sttt |
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6 |
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4 |
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320-341 |
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In this paper we show that statistical properties of the transition graph of a system to be verified can be exploited to improve memory or time performances of verification algorithms. We show experimentally that protocols exhibit transition locality. That is, with respect to levels of a breadth-first state space exploration, state transitions tend to be between states belonging to close levels of the transition graph. We support our claim by measuring transition locality for the set of protocols included in the Mur$\varphi$ verifier distribution. We present a cache-based verification algorithm that exploits transition locality to decrease memory usage and a disk-based verification algorithm that exploits transition locality to decrease disk read accesses, thus reducing the time overhead due to disk usage. Both algorithms have been implemented within the Mur$\varphi$ verifier. Our experimental results show that our cache-based algorithm can typically save more than 40% of memory with an average time penalty of about 50% when using (Mur$\varphi$) bit compression and 100% when using bit compression and hash compaction, whereas our disk-based verification algorithm is typically more than ten times faster than a previously proposed disk-based verification algorithm and, even when using 10% of the memory needed to complete verification, it is only between 40 and 530% (300% on average) slower than (RAM) Mur$\varphi$ with enough memory to complete the verification task at hand. Using just 300 MB of memory our disk-based Mur$\varphi$ was able to complete verification of a protocol with about $10^9$ reachable states. This would require more than 5 GB of memory using standard Mur$\varphi$. |
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Sapienza @ mari @ DIMTZ04j |
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91 |
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