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Author Mancini, Toni; Mari, Federico; Massini, Annalisa; Melatti, Igor; Tronci, Enrico pdf  url
doi  openurl
  Title (down) Simulator Semantics for System Level Formal Verification Type Conference Article
  Year 2015 Publication Proceedings Sixth International Symposium on Games, Automata, Logics and Formal Verification (GandALF 2015), Abbreviated Journal  
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  Area Expedition Conference  
  Notes Approved no  
  Call Number MCLab @ davi @ Serial 125  
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Author Bobbio, Andrea; Ciancamerla, Ester; Di Blasi, Saverio; Iacomini, Alessandro; Mari, Federico; Melatti, Igor; Minichino, Michele; Scarlatti, Alessandro; Tronci, Enrico; Terruggia, Roberta; Zendri, Emilio pdf  doi
openurl 
  Title (down) Risk analysis via heterogeneous models of SCADA interconnecting Power Grids and Telco networks Type Conference Article
  Year 2009 Publication Proceedings of Fourth International Conference on Risks and Security of Internet and Systems (CRiSIS) Abbreviated Journal  
  Volume Issue Pages 90-97  
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  Abstract The automation of power grids by means of supervisory control and data acquisition (SCADA) systems has led to an improvement of power grid operations and functionalities but also to pervasive cyber interdependencies between power grids and telecommunication networks. Many power grid services are increasingly depending upon the adequate functionality of SCADA system which in turn strictly depends on the adequate functionality of its communication infrastructure. We propose to tackle the SCADA risk analysis by means of different and heterogeneous modeling techniques and software tools. We demonstrate the applicability of our approach through a case study on an actual SCADA system for an electrical power distribution grid. The modeling techniques we discuss aim at providing a probabilistic dependability analysis, followed by a worst case analysis in presence of malicious attacks and a real-time performance evaluation.  
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  Area Expedition Conference Fourth International Conference on Risks and Security of Internet and Systems (CRiSIS)  
  Notes Approved yes  
  Call Number Sapienza @ mari @ crisis09 Serial 17  
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Author Hayes, B. P. ; Melatti, I.; Mancini, T.; Prodanovic, M.; Tronci, E. pdf  url
doi  openurl
  Title (down) Residential Demand Management using Individualised Demand Aware Price Policies Type Journal Article
  Year 2017 Publication IEEE Transactions On Smart Grid Abbreviated Journal  
  Volume 8 Issue 3 Pages 1284-1294  
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  Notes Approved no  
  Call Number MCLab @ davi @ Serial 157  
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Author Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico url  openurl
  Title (down) Quantized Feedback Control Software Synthesis from System Level Formal Specifications for Buck DC/DC Converters Type Report
  Year 2011 Publication Abbreviated Journal  
  Volume abs/1105.5640 Issue Pages  
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  Abstract Many Embedded Systems are indeed Software Based Control Systems (SBCSs), that is control systems whose controller consists of control software running on a microcontroller device. This motivates investigation on Formal Model Based Design approaches for automatic synthesis of SBCS control software. In previous works we presented an algorithm, along with a tool QKS implementing it, that from a formal model (as a Discrete Time Linear Hybrid System, DTLHS) of the controlled system (plant), implementation specifications (that is, number of bits in the Analog-to-Digital, AD, conversion) and System Level Formal Specifications (that is, safety and liveness requirements for the closed loop system) returns correct-by-construction control software that has a Worst Case Execution Time (WCET) linear in the number of AD bits and meets the given specifications. In this technical report we present full experimental results on using it to synthesize control software for two versions of buck DC-DC converters (single-input and multi-input), a widely used mixed-mode analog circuit.  
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  Publisher CoRR, Technical Report Place of Publication Editor  
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  Notes Approved yes  
  Call Number Sapienza @ mari @ Serial 106  
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Author Tronci, E.; Mancini, T.; Salvo, I.; Mari, F.; Melatti, I.; Massini, A.; Sinisi, S.; Davì, F.; Dierkes, T.; Ehrig, R.; Röblitz, S.; Leeners, B.; Krüger, T.; Egli, M.; Ille, F. pdf  doi
openurl 
  Title (down) Patient-Specific Models from Inter-Patient Biological Models and Clinical Records Type Conference Article
  Year 2014 Publication Formal Methods in Computer-Aided Design (FMCAD) Abbreviated Journal  
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  Notes Approved no  
  Call Number Sapienza @ mari @ Serial 120  
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Author Mancini, T.; Mari, F.; Melatti, I.; Salvo, I.; Tronci, E.; Gruber, J.; Hayes, B.; Prodanovic, M.; Elmegaard, L. pdf  doi
openurl 
  Title (down) Parallel Statistical Model Checking for Safety Verification in Smart Grids Type Conference Article
  Year 2018 Publication 2018 IEEE International Conference on Communications, Control, and Computing Technologies for Smart Grids (SmartGridComm) Abbreviated Journal  
  Volume Issue Pages 1-6  
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  Notes Approved no  
  Call Number MCLab @ davi @ mancini-etal:2018:smartgridcomm Serial 170  
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Author Melatti, Igor; Palmer, Robert; Sawaya, Geoffrey; Yang, Yu; Kirby, Robert Mike; Gopalakrishnan, Ganesh pdf  doi
openurl 
  Title (down) Parallel and distributed model checking in Eddy Type Journal Article
  Year 2009 Publication Int. J. Softw. Tools Technol. Transf. Abbreviated Journal  
  Volume 11 Issue 1 Pages 13-25  
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  Abstract Model checking of safety properties can be scaled up by pooling the CPU and memory resources of multiple computers. As compute clusters containing 100s of nodes, with each node realized using multi-core (e.g., 2) CPUs will be widespread, a model checker based on the parallel (shared memory) and distributed (message passing) paradigms will more efficiently use the hardware resources. Such a model checker can be designed by having each node employ two shared memory threads that run on the (typically) two CPUs of a node, with one thread responsible for state generation, and the other for efficient communication, including (1) performing overlapped asynchronous message passing, and (2) aggregating the states to be sent into larger chunks in order to improve communication network utilization. We present the design details of such a novel model checking architecture called Eddy. We describe the design rationale, details of how the threads interact and yield control, exchange messages, as well as detect termination. We have realized an instance of this architecture for the Murphi modeling language. Called Eddy_Murphi, we report its performance over the number of nodes as well as communication parameters such as those controlling state aggregation. Nearly linear reduction of compute time with increasing number of nodes is observed. Our thread task partition is done in such a way that it is modular, easy to port across different modeling languages, and easy to tune across a variety of platforms.  
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  Corporate Author Thesis  
  Publisher Springer-Verlag Place of Publication Berlin, Heidelberg Editor  
  Language Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 1433-2779 ISBN Medium  
  Area Expedition Conference  
  Notes Approved yes  
  Call Number Sapienza @ mari @ Mpsykg09 Serial 80  
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Author Melatti, Igor; Palmer, Robert; Sawaya, Geoffrey; Yang, Yu; Kirby, Robert Mike; Gopalakrishnan, Ganesh pdf  doi
isbn  openurl
  Title (down) Parallel and Distributed Model Checking in Eddy Type Conference Article
  Year 2006 Publication Model Checking Software, 13th International SPIN Workshop, Vienna, Austria, March 30 – April 1, 2006, Proceedings Abbreviated Journal  
  Volume Issue Pages 108-125  
  Keywords  
  Abstract Model checking of safety properties can be scaled up by pooling the CPU and memory resources of multiple computers. As compute clusters containing 100s of nodes, with each node realized using multi-core (e.g., 2) CPUs will be widespread, a model checker based on the parallel (shared memory) and distributed (message passing) paradigms will more efficiently use the hardware resources. Such a model checker can be designed by having each node employ two shared memory threads that run on the (typically) two CPUs of a node, with one thread responsible for state generation, and the other for efficient communication, including (i) performing overlapped asynchronous message passing, and (ii) aggregating the states to be sent into larger chunks in order to improve communication network utilization. We present the design details of such a novel model checking architecture called Eddy. We describe the design rationale, details of how the threads interact and yield control, exchange messages, as well as detect termination. We have realized an instance of this architecture for the Murphi modeling language. Called Eddy_Murphi, we report its performance over the number of nodes as well as communication parameters such as those controlling state aggregation. Nearly linear reduction of compute time with increasing number of nodes is observed. Our thread task partition is done in such a way that it is modular, easy to port across different modeling languages, and easy to tune across a variety of platforms.  
  Address  
  Corporate Author Thesis  
  Publisher Springer - Verlag Place of Publication Editor Valmari, A.  
  Language Summary Language Original Title  
  Series Editor Series Title Lecture Notes in Computer Science Abbreviated Series Title  
  Series Volume 3925 Series Issue Edition  
  ISSN 0302-9743 ISBN 978-3-540-33102-5 Medium  
  Area Expedition Conference  
  Notes Approved yes  
  Call Number Sapienza @ mari @ Mpsykg06 Serial 81  
Permanent link to this record
 

 
Author Alimguzhin, Vadim; Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico pdf  doi
isbn  openurl
  Title (down) On-the-Fly Control Software Synthesis Type Conference Article
  Year 2013 Publication Proceedings of International SPIN Symposium on Model Checking of Software (SPIN 2013) Abbreviated Journal International SPIN Symposium on Model Checking of Software  
  Volume Issue Pages 61-80  
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  Publisher Springer - Verlag Place of Publication Editor  
  Language Summary Language Original Title  
  Series Editor Series Title Lecture Notes in Computer Science Abbreviated Series Title  
  Series Volume 7976 Series Issue Edition  
  ISSN 0302-9743 ISBN 978-3-642-39175-0 Medium  
  Area Expedition Conference  
  Notes Approved yes  
  Call Number Sapienza @ melatti @ Serial 111  
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Author Alimguzhin, Vadim; Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico url  openurl
  Title (down) On Model Based Synthesis of Embedded Control Software Type Report
  Year 2012 Publication Abbreviated Journal  
  Volume abs/1207.4474 Issue Pages  
  Keywords  
  Abstract Many Embedded Systems are indeed Software Based Control Systems (SBCSs), that is control systems whose controller consists of control software running on a microcontroller device. This motivates investigation on Formal Model Based Design approaches for control software. Given the formal model of a plant as a Discrete Time Linear Hybrid System and the implementation specifications (that is, number of bits in the Analog-to-Digital (AD) conversion) correct-by-construction control software can be automatically generated from System Level Formal Specifications of the closed loop system (that is, safety and liveness requirements), by computing a suitable finite abstraction of the plant.
With respect to given implementation specifications, the automatically generated code implements a time optimal control strategy (in terms of set-up time), has a Worst Case Execution Time linear in the number of AD bits $b$, but unfortunately, its size grows exponentially with respect to $b$. In many embedded systems, there are severe restrictions on the computational resources (such as memory or computational power) available to microcontroller devices.
This paper addresses model based synthesis of control software by trading system level non-functional requirements (such us optimal set-up time, ripple) with software non-functional requirements (its footprint). Our experimental results show the effectiveness of our approach: for the inverted pendulum benchmark, by using a quantization schema with 12 bits, the size of the small controller is less than 6% of the size of the time optimal one.
 
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  Publisher CoRR, Technical Report Place of Publication Editor  
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  ISSN ISBN Medium  
  Area Expedition Conference  
  Notes Approved yes  
  Call Number Sapienza @ mari @ Serial 102  
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