| Records |
| Author |
Focardi, Riccardo; Gorrieri, Roberto; Lanotte, Ruggero; Maggiolo-Schettini, Andrea; Martinelli, Fabio; Tini, Simone; Tronci, Enrico |
| Title |
Formal Models of Timing Attacks on Web Privacy |
Type |
Journal Article |
| Year |
2002 |
Publication |
Electronic Notes in Theoretical Computer Science |
Abbreviated Journal |
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| Volume |
62 |
Issue |
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Pages |
229-243 |
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| Abstract |
We model a timing attack on web privacy proposed by Felten and Schneider by using three different approaches: HL-Timed Automata, SMV model checker, and tSPA Process Algebra. Some comparative analysis on the three approaches is derived. |
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TOSCA 2001, Theory of Concurrency, Higher Order Languages and Types |
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yes |
| Call Number |
Sapienza @ mari @ entcs02a |
Serial |
47 |
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| Author |
Barbanera, Franco; Dezani-Ciancaglini, Mariangiola; Salvo, Ivano; Sassone, Vladimiro |
| Title |
A Type Inference Algorithm for Secure Ambients |
Type |
Journal Article |
| Year |
2002 |
Publication |
Electronic Notes in Theoretical Computer Science |
Abbreviated Journal |
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| Volume |
62 |
Issue |
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Pages |
83-101 |
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| Abstract |
We consider a type discipline for the Ambient Calculus that associates ambients with security levels and constrains them to be traversed by or opened in ambients of higher security clearance only. We present a bottom-up algorithm that, given an untyped process P, computes a minimal set of constraints on security levels such that all actions during runs of P are performed without violating the security level priorities. Such an algorithm appears to be a prerequisite to use type systems to ensure security properties in the web scenario. |
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Elsevier |
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TOSCA 2001, Theory of Concurrency, Higher Order Languages and Types |
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yes |
| Call Number |
Sapienza @ mari @ Barbanera-Dezani-Salvo-Sassone:01 |
Serial |
73 |
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| Author |
Lanotte, Ruggero; Maggiolo-Schettini, Andrea; Tini, Simone; Troina, Angelo; Tronci, Enrico |
| Title |
Automatic Analysis of the NRL Pump |
Type |
Journal Article |
| Year |
2004 |
Publication |
Electr. Notes Theor. Comput. Sci. |
Abbreviated Journal |
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| Volume |
99 |
Issue |
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Pages |
245-266 |
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We define a probabilistic model for the NRL Pump and using FHP-mur$\varphi$ show experimentally that there exists a probabilistic covert channel whose capacity depends on various NRL Pump parameters (e.g. buffer size, number of samples in the moving average, etc). |
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yes |
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Sapienza @ mari @ entcs04 |
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36 |
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| Author |
Tronci, Enrico |
| Title |
Equational Programming in Lambda-Calculus via SL-Systems. Part 2 |
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Journal Article |
| Year |
1996 |
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Theoretical Computer Science |
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160 |
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1&2 |
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185-216 |
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yes |
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Sapienza @ mari @ tcs96a |
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55 |
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| Author |
Tronci, Enrico |
| Title |
Equational Programming in Lambda-Calculus via SL-Systems. Part 1 |
Type |
Journal Article |
| Year |
1996 |
Publication |
Theoretical Computer Science |
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160 |
Issue |
1&2 |
Pages |
145-184 |
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yes |
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Sapienza @ mari @ tcs96 |
Serial |
54 |
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| Author |
Gorrieri, Roberto; Lanotte, Ruggero; Maggiolo-Schettini, Andrea; Martinelli, Fabio; Tini, Simone; Tronci, Enrico |
| Title |
Automated analysis of timed security: a case study on web privacy |
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Journal Article |
| Year |
2004 |
Publication |
International Journal of Information Security |
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2 |
Issue |
3-4 |
Pages |
168-186 |
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| Abstract |
This paper presents a case study on an automated analysis of real-time security models. The case study on a web system (originally proposed by Felten and Schneider) is presented that shows a timing attack on the privacy of browser users. Three different approaches are followed: LH-Timed Automata (analyzed using the model checker HyTech), finite-state automata (analyzed using the model checker NuSMV), and process algebras (analyzed using the model checker CWB-NC). A comparative analysis of these three approaches is given. |
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yes |
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Sapienza @ mari @ ijis04 |
Serial |
33 |
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| Author |
Della Penna, Giuseppe; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico; Venturini Zilli, Marisa |
| Title |
Finite horizon analysis of Markov Chains with the Mur$\varphi$ verifier |
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Journal Article |
| Year |
2006 |
Publication |
Int. J. Softw. Tools Technol. Transf. |
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8 |
Issue |
4 |
Pages |
397-409 |
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In this paper we present an explicit disk-based verification algorithm for Probabilistic Systems defining discrete time/finite state Markov Chains. Given a Markov Chain and an integer k (horizon), our algorithm checks whether the probability of reaching an error state in at most k steps is below a given threshold. We present an implementation of our algorithm within a suitable extension of the Mur$\varphi$ verifier. We call the resulting probabilistic model checker FHP-Mur$\varphi$ (Finite Horizon Probabilistic Mur$\varphi$). We present experimental results comparing FHP-Mur$\varphi$ with (a finite horizon subset of) PRISM, a state-of-the-art symbolic model checker for Markov Chains. Our experimental results show that FHP-Mur$\varphi$ can handle systems that are out of reach for PRISM, namely those involving arithmetic operations on the state variables (e.g. hybrid systems). |
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Springer-Verlag |
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Berlin, Heidelberg |
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1433-2779 |
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yes |
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Sapienza @ mari @ Dimtz06 |
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78 |
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| Author |
Tronci, Enrico |
| Title |
Introductory Paper |
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Journal Article |
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2006 |
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Sttt |
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8 |
Issue |
4-5 |
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355-358 |
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In today’s competitive market designing of digital systems (hardware as well as software) faces tremendous challenges. In fact, notwithstanding an ever decreasing project budget, time to market and product lifetime, designers are faced with an ever increasing system complexity and customer expected quality. The above situation calls for better and better formal verification techniques at all steps of the design flow. This special issue is devoted to publishing revised versions of contributions first presented at the 12th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME) held 21–24 October 2003 in L’Aquila, Italy. Authors of well regarded papers from CHARME’03 were invited to submit to this special issue. All papers included here have been suitably extended and have undergone an independent round of reviewing. |
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yes |
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Sapienza @ mari @ sttt06 |
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30 |
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| Author |
Della Penna, Giuseppe; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico; Venturini Zilli, Marisa |
| Title |
Exploiting Transition Locality in Automatic Verification of Finite State Concurrent Systems |
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Journal Article |
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2004 |
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Sttt |
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6 |
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4 |
Pages |
320-341 |
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In this paper we show that statistical properties of the transition graph of a system to be verified can be exploited to improve memory or time performances of verification algorithms. We show experimentally that protocols exhibit transition locality. That is, with respect to levels of a breadth-first state space exploration, state transitions tend to be between states belonging to close levels of the transition graph. We support our claim by measuring transition locality for the set of protocols included in the Mur$\varphi$ verifier distribution. We present a cache-based verification algorithm that exploits transition locality to decrease memory usage and a disk-based verification algorithm that exploits transition locality to decrease disk read accesses, thus reducing the time overhead due to disk usage. Both algorithms have been implemented within the Mur$\varphi$ verifier. Our experimental results show that our cache-based algorithm can typically save more than 40% of memory with an average time penalty of about 50% when using (Mur$\varphi$) bit compression and 100% when using bit compression and hash compaction, whereas our disk-based verification algorithm is typically more than ten times faster than a previously proposed disk-based verification algorithm and, even when using 10% of the memory needed to complete verification, it is only between 40 and 530% (300% on average) slower than (RAM) Mur$\varphi$ with enough memory to complete the verification task at hand. Using just 300 MB of memory our disk-based Mur$\varphi$ was able to complete verification of a protocol with about $10^9$ reachable states. This would require more than 5 GB of memory using standard Mur$\varphi$. |
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yes |
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Sapienza @ mari @ DIMTZ04j |
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91 |
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| Author |
Bucciarelli, Antonio; Salvo, Ivano |
| Title |
Totality, Definability and Boolean Circuits |
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Journal Article |
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1998 |
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1443 |
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808-819 |
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In the type frame originating from the flat domain of boolean values, we single out elements which are hereditarily total. We show that these elements can be defined, up to total equivalence, by sequential programs. The elements of an equivalence class of the totality equivalence relation (totality class) can be seen as different algorithms for computing a given set-theoretic boolean function. We show that the bottom element of a totality class, which is sequential, corresponds to the most eager algorithm, and the top to the laziest one. Finally we suggest a link between size of totality classes and a well known measure of complexity of boolean functions, namely their sensitivity. |
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Springer |
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yes |
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Sapienza @ mari @ bucciarelli-salvo:98 |
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70 |
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