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Author |
Alimguzhin, Vadim; Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Title |
On Model Based Synthesis of Embedded Control Software |
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Conference Article |
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Year |
2012 |
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Proceedings of the 12th International Conference on Embedded Software, EMSOFT 2012, part of the Eighth Embedded Systems Week, ESWeek 2012, Tampere, Finland, October 7-12, 2012 |
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227-236 |
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ACM |
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Ahmed Jerraya and Luca P. Carloni and Florence Maraninchi and John Regehr |
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978-1-4503-1425-1 |
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Techreport version can be found at arxiv.org |
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yes |
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Call Number  |
Sapienza @ mari @ emsoft12 |
Serial |
97 |
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Author |
Della Penna, Giuseppe; Intrigila, Benedetto; Tronci, Enrico; Venturini Zilli, Marisa |
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Title |
Synchronized Regular Expressions |
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Journal Article |
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Year |
2002 |
Publication |
Electr. Notes Theor. Comput. Sci. |
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62 |
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195-210 |
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Abstract |
Text manipulation is one of the most common tasks for everyone using a computer. The increasing number of textual information in electronic format that every computer user collects everyday stresses the need of more powerful tools to interact with texts. Indeed, much work has been done to provide nonprogramming tools that can be useful for the most common text manipulation issues. Regular Expressions (RE), introduced by Kleene, are well–known in the formal language theory. RE received several extensions, depending on the application of interest. In almost all the implementations of RE search algorithms (e.g. the egrep [A] UNIX command, or the Perl [17] language pattern matching constructs) we find backreferences (as defind in [1]), i.e. expressions that make reference to the string matched by a previous subexpression. Generally speaking, it seems that all the kinds of synchronizations between subexpressions in a RE can be very useful when interacting with texts. Therefore, we introduce the Synchronized Regular Expressions (SRE) as a derivation of the Regular Expressions. We use SRE to present a formal study of the already known backreferences extension, and of a new extension proposed by us, which we call the synchronized exponents. Moreover, since we are talking about formalisms that should have a practical utility and can be used in the real world, we have the problem of how to present SRE to the final users. Therefore, in this paper we also propose a user–friendly syntax for SRE to be used in implementations of SRE–powered search algorithms. |
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TOSCA 2001, Theory of Concurrency, Higher Order Languages and Types |
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yes |
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Call Number |
Sapienza @ mari @ entcs02 |
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46 |
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Author |
Della Penna, Giuseppe; Intrigila, Benedetto; Tronci, Enrico; Venturini Zilli, Marisa |
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Title |
Exploiting Transition Locality in the Disk Based Mur$\varphi$ Verifier |
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Conference Article |
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2002 |
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4th International Conference on Formal Methods in Computer-Aided Design (FMCAD) |
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202-219 |
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The main obstruction to automatic verification of Finite State Systems is the huge amount of memory required to complete the verification task (state explosion). This motivates research on distributed as well as disk based verification algorithms. In this paper we present a disk based Breadth First Explicit State Space Exploration algorithm as well as an implementation of it within the Mur$\varphi$ verifier. Our algorithm exploits transition locality (i.e. the statistical fact that most transitions lead to unvisited states or to recently visited states) to decrease disk read accesses thus reducing the time overhead due to disk usage. A disk based verification algorithm for Mur$\varphi$ has been already proposed in the literature. To measure the time speed up due to locality exploitation we compared our algorithm with such previously proposed algorithm. Our experimental results show that our disk based verification algorithm is typically more than 10 times faster than such previously proposed disk based verification algorithm. To measure the time overhead due to disk usage we compared our algorithm with RAM based verification using the (standard) Mur$\varphi$ verifier with enough memory to complete the verification task. Our experimental results show that even when using 1/10 of the RAM needed to complete verification, our disk based algorithm is only between 1.4 and 5.3 times (3 times on average) slower than (RAM) Mur$\varphi$ with enough RAM memory to complete the verification task at hand. Using our disk based Mur$\varphi$ we were able to complete verification of a protocol with about $10^9$ reachable states. This would require more than 5 gigabytes of RAM using RAM based Mur$\varphi$. |
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Springer |
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Portland, OR, USA |
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Aagaard, M.; O'Leary, J.W. |
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Lecture Notes in Computer Science |
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Series Volume |
2517 |
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3-540-00116-6 |
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yes |
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Sapienza @ mari @ fmcad02 |
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41 |
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Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Title |
From Boolean Relations to Control Software |
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Conference Article |
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2011 |
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Proceedings of ICSEA 2011, The Sixth International Conference on Software Engineering Advances |
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528-533 |
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Many software as well digital hardware automatic synthesis methods define the set of implementations meeting the given system specifications with a boolean relation K. In such a context a fundamental step in the software (hardware) synthesis process is finding effective solutions to the functional equation defined by K. This entails finding a (set of) boolean function(s) F (typically represented using OBDDs, Ordered Binary Decision Diagrams) such that: 1) for all x for which K is satisfiable, K(x, F(x)) = 1 holds; 2) the implementation of F is efficient with respect to given implementation parameters such as code size or execution time. While this problem has been widely studied in digital hardware synthesis, little has been done in a software synthesis context. Unfortunately the approaches developed for hardware synthesis cannot be directly used in a software context. This motivates investigation of effective methods to solve the above problem when F has to be implemented with software. In this paper we present an algorithm that, from an OBDD representation for K, generates a C code implementation for F that has the same size as the OBDD for F and a WCET (Worst Case Execution Time) linear in nr, being n = |x| the number of input arguments for functions in F and r the number of functions in F. |
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ThinkMind |
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978-1-61208-165-6 |
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Best Paper Award |
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yes |
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Call Number |
Sapienza @ mari @ icsea11 |
Serial |
14 |
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Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Title |
Linear Constraints as a Modeling Language for Discrete Time Hybrid Systems |
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Conference Article |
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2012 |
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Proceedings of ICSEA 2012, The Seventh International Conference on Software Engineering Advances |
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664-671 |
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ThinkMind |
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yes |
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Call Number |
Sapienza @ mari @ icsea12 |
Serial |
98 |
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Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Title |
Control Software Visualization |
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Conference Article |
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Year |
2012 |
Publication |
Proceedings of INFOCOMP 2012, The Second International Conference on Advanced Communications and Computation |
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15-20 |
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ThinkMind |
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978-1-61208-226-4 |
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yes |
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Sapienza @ mari @ infocomp2012 |
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100 |
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Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Title |
Undecidability of Quantized State Feedback Control for Discrete Time Linear Hybrid Systems |
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Book Chapter |
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Year |
2012 |
Publication |
Theoretical Aspects of Computing – ICTAC 2012 |
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243-258 |
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Springer Berlin Heidelberg |
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Roychoudhury, A.; D'Souza, M. |
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Lecture Notes in Computer Science |
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7521 |
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978-3-642-32942-5 |
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yes |
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Call Number |
Sapienza @ mari @ Mari2012 |
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99 |
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Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico; Alvisi, Lorenzo; Clement, Allen; Li, Harry |
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Title |
Model Checking Nash Equilibria in MAD Distributed Systems |
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Conference Article |
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2008 |
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FMCAD '08: Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design |
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1-8 |
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Model Checking, MAD Distributed System, Nash Equilibrium |
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We present a symbolic model checking algorithm for verification of Nash equilibria in finite state mechanisms modeling Multiple Administrative Domains (MAD) distributed systems. Given a finite state mechanism, a proposed protocol for each agent and an indifference threshold for rewards, our model checker returns PASS if the proposed protocol is a Nash equilibrium (up to the given indifference threshold) for the given mechanism, FAIL otherwise. We implemented our model checking algorithm inside the NuSMV model checker and present experimental results showing its effectiveness for moderate size mechanisms. For example, we can handle mechanisms which corresponding normal form games would have more than $10^20$ entries. To the best of our knowledge, no model checking algorithm for verification of mechanism Nash equilibria has been previously published. |
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IEEE Press |
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Piscataway, NJ, USA |
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Cimatti, A.; Jones, R. |
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978-1-4244-2735-2 |
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yes |
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Call Number |
Sapienza @ mari @ MarMelSalTroAlvCle08 |
Serial |
93 |
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Author |
Mari, Federico; Tronci, Enrico |
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Title |
CEGAR Based Bounded Model Checking of Discrete Time Hybrid Systems |
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Conference Article |
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Year |
2007 |
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Hybrid Systems: Computation and Control (HSCC 2007) |
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399-412 |
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Model Checking, Abstraction, CEGAR, SAT, Hybrid Systems, DTHS |
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Many hybrid systems can be conveniently modeled as Piecewise Affine Discrete Time Hybrid Systems PA-DTHS. As well known Bounded Model Checking (BMC) for such systems comes down to solve a Mixed Integer Linear Programming (MILP) feasibility problem. We present a SAT based BMC algorithm for automatic verification of PA-DTHSs. Using Counterexample Guided Abstraction Refinement (CEGAR) our algorithm gradually transforms a PA-DTHS verification problem into larger and larger SAT problems. Our experimental results show that our approach can handle PA-DTHSs that are more then 50 times larger than those that can be handled using a MILP solver. |
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Springer |
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Bemporad, A.; Bicchi, A.; Buttazzo, G.C. |
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Lecture Notes in Computer Science |
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4416 |
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yes |
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Sapienza @ mari @ MarTro07 |
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92 |
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Author |
Alimguzhin, V.; Mari, F.; Melatti, I.; Salvo, I.; Tronci, E. |
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Title |
Linearising Discrete Time Hybrid Systems |
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Journal Article |
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Year |
2017 |
Publication |
IEEE Transactions on Automatic Control |
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62 |
Issue |
10 |
Pages |
5357-5364 |
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Abstract |
Model Based Design approaches for embedded systems aim at generating correct-by-construction control software, guaranteeing that the closed loop system (controller and plant) meets given system level formal specifications. This technical note addresses control synthesis for safety and reachability properties of possibly non-linear discrete time hybrid systems. By means of syntactical transformations that require non-linear terms to be Lipschitz continuous functions, we over-approximate non-linear dynamics with a linear system whose controllers are guaranteed to be controllers of the original system. We evaluate performance of our approach on meaningful control synthesis benchmarks, also comparing it to a state-of-the-art tool. |
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0018-9286 |
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no |
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Sapienza @ mari @ ref7902199 |
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164 |
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