| Home | << 1 2 3 4 5 6 7 >> |
|
| Records | |||||
|---|---|---|---|---|---|
| Author | Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico | ||||
| Title | Model Based Synthesis of Control Software from System Level Formal Specifications | Type | Journal Article | ||
| Year | 2014 | Publication  |
ACM TRANSACTIONS ON SOFTWARE ENGINEERING AND METHODOLOGY | Abbreviated Journal | ACM TRANSACTIONS ON SOFTWARE ENGINEERING AND METHODOLOGY |
| Volume | 23 | Issue | 1 | Pages | Article 6 |
| Keywords | |||||
| Abstract | |||||
| Address | |||||
| Corporate Author | Thesis | ||||
| Publisher | ACM | Place of Publication | Editor | ||
| Language | Summary Language | Original Title | |||
| Series Editor | Series Title | Abbreviated Series Title | |||
| Series Volume | Series Issue | Edition | |||
| ISSN | 1049-331X | ISBN | Medium | ||
| Area | Expedition | Conference | |||
| Notes | Approved | no | |||
| Call Number | Sapienza @ melatti @ | Serial | 110 | ||
| Permanent link to this record | |||||
| Author | Tronci, Enrico; Della Penna, Giuseppe; Intrigila, Benedetto; Venturini Zilli, Marisa | ||||
| Title | A Probabilistic Approach to Automatic Verification of Concurrent Systems | Type | Conference Article | ||
| Year | 2001 | Publication |
8th Asia-Pacific Software Engineering Conference (APSEC) | Abbreviated Journal | |
| Volume | Issue | Pages | 317-324 | ||
| Keywords | |||||
| Abstract | The main barrier to automatic verification of concurrent systems is the huge amount of memory required to complete the verification task (state explosion). In this paper we present a probabilistic algorithm for automatic verification via model checking. Our algorithm trades space with time. In particular, when memory is full because of state explosion our algorithm does not give up verification. Instead it just proceeds at a lower speed and its results will only hold with some arbitrarily small error probability. Our preliminary experimental results show that by using our probabilistic algorithm we can typically save more than 30% of RAM with an average time penalty of about 100% w.r.t. a deterministic state space exploration with enough memory to complete the verification task. This is better than giving up the verification task because of lack of memory. | ||||
| Address | |||||
| Corporate Author | Thesis | ||||
| Publisher | IEEE Computer Society | Place of Publication | Macau, China | Editor | |
| Language | Summary Language | Original Title | |||
| Series Editor | Series Title | Abbreviated Series Title | |||
| Series Volume | Series Issue | Edition | |||
| ISSN | 0-7695-1408-1 | ISBN | Medium | ||
| Area | Expedition | Conference | |||
| Notes | Approved | yes | |||
| Call Number | Sapienza @ mari @ apsec01 | Serial | 43 | ||
| Permanent link to this record | |||||
| Author | Della Penna, Giuseppe; Intrigila, Benedetto; Tronci, Enrico; Venturini Zilli, Marisa | ||||
| Title | Exploiting Transition Locality in the Disk Based Mur$\varphi$ Verifier | Type | Conference Article | ||
| Year | 2002 | Publication |
4th International Conference on Formal Methods in Computer-Aided Design (FMCAD) | Abbreviated Journal | |
| Volume | Issue | Pages | 202-219 | ||
| Keywords | |||||
| Abstract | The main obstruction to automatic verification of Finite State Systems is the huge amount of memory required to complete the verification task (state explosion). This motivates research on distributed as well as disk based verification algorithms. In this paper we present a disk based Breadth First Explicit State Space Exploration algorithm as well as an implementation of it within the Mur$\varphi$ verifier. Our algorithm exploits transition locality (i.e. the statistical fact that most transitions lead to unvisited states or to recently visited states) to decrease disk read accesses thus reducing the time overhead due to disk usage. A disk based verification algorithm for Mur$\varphi$ has been already proposed in the literature. To measure the time speed up due to locality exploitation we compared our algorithm with such previously proposed algorithm. Our experimental results show that our disk based verification algorithm is typically more than 10 times faster than such previously proposed disk based verification algorithm. To measure the time overhead due to disk usage we compared our algorithm with RAM based verification using the (standard) Mur$\varphi$ verifier with enough memory to complete the verification task. Our experimental results show that even when using 1/10 of the RAM needed to complete verification, our disk based algorithm is only between 1.4 and 5.3 times (3 times on average) slower than (RAM) Mur$\varphi$ with enough RAM memory to complete the verification task at hand. Using our disk based Mur$\varphi$ we were able to complete verification of a protocol with about $10^9$ reachable states. This would require more than 5 gigabytes of RAM using RAM based Mur$\varphi$. | ||||
| Address | |||||
| Corporate Author | Thesis | ||||
| Publisher | Springer | Place of Publication | Portland, OR, USA | Editor | Aagaard, M.; O'Leary, J.W. |
| Language | Summary Language | Original Title | |||
| Series Editor | Series Title | Lecture Notes in Computer Science | Abbreviated Series Title | ||
| Series Volume | 2517 | Series Issue | Edition | ||
| ISSN | 3-540-00116-6 | ISBN | Medium | ||
| Area | Expedition | Conference | |||
| Notes | Approved | yes | |||
| Call Number | Sapienza @ mari @ fmcad02 | Serial | 41 | ||
| Permanent link to this record | |||||
| Author | Mancini, T.; Mari, F.; Massini, A.; Melatti, I.; Salvo, I.; Sinisi, S.; Tronci, E.; Ehrig, R.; Röblitz, S.; Leeners, B. | ||||
| Title | Computing Personalised Treatments through In Silico Clinical Trials. A Case Study on Downregulation in Assisted Reproduction | Type | Conference Article | ||
| Year | 2018 | Publication |
25th RCRA International Workshop on “Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion” (RCRA 2018) | Abbreviated Journal | |
| Volume | Issue | Pages | |||
| Keywords | |||||
| Abstract | |||||
| Address | |||||
| Corporate Author | Thesis | ||||
| Publisher | Place of Publication | Editor | |||
| Language | Summary Language | Original Title | |||
| Series Editor | Series Title | Abbreviated Series Title | |||
| Series Volume | Series Issue | Edition | |||
| ISSN | ISBN | Medium | |||
| Area | Expedition | Conference | |||
| Notes | Approved | no | |||
| Call Number | MCLab @ davi @ | Serial | 175 | ||
| Permanent link to this record | |||||
| Author | Mancini, T.; Mari, F.; Melatti, I.; Salvo, I.; Tronci, E.; Gruber, J.; Hayes, B.; Prodanovic, M.; Elmegaard, L. | ||||
| Title | Parallel Statistical Model Checking for Safety Verification in Smart Grids | Type | Conference Article | ||
| Year | 2018 | Publication |
2018 IEEE International Conference on Communications, Control, and Computing Technologies for Smart Grids (SmartGridComm) | Abbreviated Journal | |
| Volume | Issue | Pages | 1-6 | ||
| Keywords | |||||
| Abstract | |||||
| Address | |||||
| Corporate Author | Thesis | ||||
| Publisher | Place of Publication | Editor | |||
| Language | Summary Language | Original Title | |||
| Series Editor | Series Title | Abbreviated Series Title | |||
| Series Volume | Series Issue | Edition | |||
| ISSN | ISBN | Medium | |||
| Area | Expedition | Conference | |||
| Notes | Approved | no | |||
| Call Number | MCLab @ davi @ mancini-etal:2018:smartgridcomm | Serial | 170 | ||
| Permanent link to this record | |||||
| Author | Tronci, Enrico; Della Penna, Giuseppe; Intrigila, Benedetto; Venturini Zilli, Marisa | ||||
| Title | Exploiting Transition Locality in Automatic Verification | Type | Conference Article | ||
| Year | 2001 | Publication |
11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME) | Abbreviated Journal | |
| Volume | Issue | Pages | 259-274 | ||
| Keywords | |||||
| Abstract | In this paper we present an algorithm to contrast state explosion when using Explicit State Space Exploration to verify protocols. We show experimentally that protocols exhibit transition locality. We present a verification algorithm that exploits transition locality as well as an implementation of it within the Mur$\varphi$ verifier. Our algorithm is compatible with all Breadth First (BF) optimization techniques present in the Mur$\varphi$ verifier and it is by no means a substitute for any of them. In fact, since our algorithm trades space with time, it is typically most useful when one runs out of memory and has already used all other state reduction techniques present in the Mur$\varphi$ verifier. Our experimental results show that using our approach we can typically save more than 40% of RAM with an average time penalty of about 50% when using (Mur$\varphi$) bit compression and 100% when using bit compression and hash compaction. | ||||
| Address | |||||
| Corporate Author | Thesis | ||||
| Publisher | Springer | Place of Publication | Livingston, Scotland, UK | Editor | Margaria, T.; Melham, T.F. |
| Language | Summary Language | Original Title | |||
| Series Editor | Series Title | Lecture Notes in Computer Science | Abbreviated Series Title | ||
| Series Volume | 2144 | Series Issue | Edition | ||
| ISSN | 3-540-42541-1 | ISBN | Medium | ||
| Area | Expedition | Conference | |||
| Notes | Approved | yes | |||
| Call Number | Sapienza @ mari @ charme01 | Serial | 44 | ||
| Permanent link to this record | |||||
| Author | Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico | ||||
| Title | Model Based Synthesis of Control Software from System Level Formal Specifications | Type | Report | ||
| Year | 2013 | Publication |
Abbreviated Journal | ||
| Volume | abs/1107.5638 | Issue | Pages | ||
| Keywords | |||||
| Abstract | Many Embedded Systems are indeed Software Based Control Systems, that is control systems whose controller consists of control software running on a microcontroller device. This motivates investigation on Formal Model Based Design approaches for automatic synthesis of embedded systems control software.
We present an algorithm, along with a tool QKS implementing it, that from a formal model (as a Discrete Time Linear Hybrid System) of the controlled system (plant), implementation specifications (that is, number of bits in the Analog-to-Digital, AD, conversion) and System Level Formal Specifications (that is, safety and liveness requirements for the closed loop system) returns correct-by-construction control software that has a Worst Case Execution Time (WCET) linear in the number of AD bits and meets the given specifications. We show feasibility of our approach by presenting experimental results on using it to synthesize control software for a buck DC-DC converter, a widely used mixed-mode analog circuit, and for the inverted pendulum. |
||||
| Address | |||||
| Corporate Author | Thesis | ||||
| Publisher | CoRR, Technical Report | Place of Publication | Editor | ||
| Language | Summary Language | Original Title | |||
| Series Editor | Series Title | Abbreviated Series Title | |||
| Series Volume | Series Issue | Edition | |||
| ISSN | ISBN | Medium | |||
| Area | Expedition | Conference | |||
| Notes | Approved | yes | |||
| Call Number | Sapienza @ mari @ | Serial | 104 | ||
| Permanent link to this record | |||||
| Author | Sinisi, S.; Alimguzhin, V.; Mancini, T.; Tronci, E.; Mari, F.; Leeners, B. | ||||
| Title | Optimal Personalised Treatment Computation through In Silico Clinical Trials on Patient Digital Twins | Type | Journal Article | ||
| Year | 2020 | Publication |
Abbreviated Journal | Fundamenta Informaticae | |
| Volume | 174 | Issue | Pages | 283-310 | |
| Keywords | Artificial Intelligence; Virtual Physiological Human; In Silico Clinical Trials; Simulation; Personalised Medicine; In Silico Treatment Optimisation | ||||
| Abstract | In Silico Clinical Trials (ISCT), i.e. clinical experimental campaigns carried out by means of computer simulations, hold the promise to decrease time and cost for the safety and efficacy assessment of pharmacological treatments, reduce the need for animal and human testing, and enable precision medicine. In this paper we present methods and an algorithm that, by means of extensive computer simulation-based experimental campaigns (ISCT) guided by intelligent search, optimise a pharmacological treatment for an individual patient (precision medicine ). We show the effectiveness of our approach on a case study involving a real pharmacological treatment, namely the downregulation phase of a complex clinical protocol for assisted reproduction in humans. | ||||
| Address | |||||
| Corporate Author | Thesis | ||||
| Publisher | IOS Press | Place of Publication | Editor | ||
| Language | Summary Language | Original Title | |||
| Series Editor | Series Title | Abbreviated Series Title | |||
| Series Volume | Series Issue | Edition | |||
| ISSN | 1875-8681 | ISBN | Medium | ||
| Area | Expedition | Conference | |||
| Notes | Approved | no | |||
| Call Number | MCLab @ davi @ | Serial | 187 | ||
| Permanent link to this record | |||||
| Author | Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico | ||||
| Title | From Boolean Functional Equations to Control Software | Type | Report | ||
| Year | 2011 | Publication |
Abbreviated Journal | ||
| Volume | abs/1106.0468 | Issue | Pages | ||
| Keywords | |||||
| Abstract | Many software as well digital hardware automatic synthesis methods define the set of implementations meeting the given system specifications with a boolean relation K. In such a context a fundamental step in the software (hardware) synthesis process is finding effective solutions to the functional equation defined by K. This entails finding a (set of) boolean function(s) F (typically represented using OBDDs, Ordered Binary Decision Diagrams) such that: 1) for all x for which K is satisfiable, K(x, F(x)) = 1 holds; 2) the implementation of F is efficient with respect to given implementation parameters such as code size or execution time. While this problem has been widely studied in digital hardware synthesis, little has been done in a software synthesis context. Unfortunately the approaches developed for hardware synthesis cannot be directly used in a software context. This motivates investigation of effective methods to solve the above problem when F has to be implemented with software. In this paper we present an algorithm that, from an OBDD representation for K, generates a C code implementation for F that has the same size as the OBDD for F and a WCET (Worst Case Execution Time) at most O(nr), being n = |x| the number of arguments of functions in F and r the number of functions in F. | ||||
| Address | |||||
| Corporate Author | Thesis | ||||
| Publisher | CoRR, Technical Report | Place of Publication | Editor | ||
| Language | Summary Language | Original Title | |||
| Series Editor | Series Title | Abbreviated Series Title | |||
| Series Volume | Series Issue | Edition | |||
| ISSN | ISBN | Medium | |||
| Area | Expedition | Conference | |||
| Notes | Approved | yes | |||
| Call Number | Sapienza @ mari @ | Serial | 105 | ||
| Permanent link to this record | |||||
| Author | Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico | ||||
| Title | Quantized Feedback Control Software Synthesis from System Level Formal Specifications for Buck DC/DC Converters | Type | Report | ||
| Year | 2011 | Publication |
Abbreviated Journal | ||
| Volume | abs/1105.5640 | Issue | Pages | ||
| Keywords | |||||
| Abstract | Many Embedded Systems are indeed Software Based Control Systems (SBCSs), that is control systems whose controller consists of control software running on a microcontroller device. This motivates investigation on Formal Model Based Design approaches for automatic synthesis of SBCS control software. In previous works we presented an algorithm, along with a tool QKS implementing it, that from a formal model (as a Discrete Time Linear Hybrid System, DTLHS) of the controlled system (plant), implementation specifications (that is, number of bits in the Analog-to-Digital, AD, conversion) and System Level Formal Specifications (that is, safety and liveness requirements for the closed loop system) returns correct-by-construction control software that has a Worst Case Execution Time (WCET) linear in the number of AD bits and meets the given specifications. In this technical report we present full experimental results on using it to synthesize control software for two versions of buck DC-DC converters (single-input and multi-input), a widely used mixed-mode analog circuit. | ||||
| Address | |||||
| Corporate Author | Thesis | ||||
| Publisher | CoRR, Technical Report | Place of Publication | Editor | ||
| Language | Summary Language | Original Title | |||
| Series Editor | Series Title | Abbreviated Series Title | |||
| Series Volume | Series Issue | Edition | |||
| ISSN | ISBN | Medium | |||
| Area | Expedition | Conference | |||
| Notes | Approved | yes | |||
| Call Number | Sapienza @ mari @ | Serial | 106 | ||
| Permanent link to this record | |||||