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Author | Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico; Alvisi, Lorenzo; Clement, Allen; Li, Harry | ||||
Title | Model Checking Nash Equilibria in MAD Distributed Systems | Type | Conference Article | ||
Year | 2008 | Publication | FMCAD '08: Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design | Abbreviated Journal | |
Volume | Issue | Pages | 1-8 | ||
Keywords | Model Checking, MAD Distributed System, Nash Equilibrium | ||||
Abstract | We present a symbolic model checking algorithm for verification of Nash equilibria in finite state mechanisms modeling Multiple Administrative Domains (MAD) distributed systems. Given a finite state mechanism, a proposed protocol for each agent and an indifference threshold for rewards, our model checker returns PASS if the proposed protocol is a Nash equilibrium (up to the given indifference threshold) for the given mechanism, FAIL otherwise. We implemented our model checking algorithm inside the NuSMV model checker and present experimental results showing its effectiveness for moderate size mechanisms. For example, we can handle mechanisms which corresponding normal form games would have more than $10^20$ entries. To the best of our knowledge, no model checking algorithm for verification of mechanism Nash equilibria has been previously published. | ||||
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Publisher | IEEE Press | Place of Publication | Piscataway, NJ, USA | Editor | Cimatti, A.; Jones, R. |
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ISSN | 978-1-4244-2735-2 | ISBN | Medium | ||
Area | Expedition | Conference | |||
Notes | Approved | yes | |||
Call Number | Sapienza @ mari @ MarMelSalTroAlvCle08 | Serial | 93 | ||
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Author | Tronci, Enrico; Della Penna, Giuseppe; Intrigila, Benedetto; Venturini Zilli, Marisa | ||||
Title | A Probabilistic Approach to Automatic Verification of Concurrent Systems | Type | Conference Article | ||
Year | 2001 | Publication | 8th Asia-Pacific Software Engineering Conference (APSEC) | Abbreviated Journal | |
Volume | Issue | Pages | 317-324 | ||
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Abstract | The main barrier to automatic verification of concurrent systems is the huge amount of memory required to complete the verification task (state explosion). In this paper we present a probabilistic algorithm for automatic verification via model checking. Our algorithm trades space with time. In particular, when memory is full because of state explosion our algorithm does not give up verification. Instead it just proceeds at a lower speed and its results will only hold with some arbitrarily small error probability. Our preliminary experimental results show that by using our probabilistic algorithm we can typically save more than 30% of RAM with an average time penalty of about 100% w.r.t. a deterministic state space exploration with enough memory to complete the verification task. This is better than giving up the verification task because of lack of memory. | ||||
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Publisher | IEEE Computer Society | Place of Publication | Macau, China | Editor | |
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ISSN | 0-7695-1408-1 | ISBN | Medium | ||
Area | Expedition | Conference | |||
Notes | Approved | yes | |||
Call Number | Sapienza @ mari @ apsec01 | Serial | 43 | ||
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Author | Mancini, Toni ; Mari, Federico ; Massini, Annalisa; Melatti, Igor; Tronci, Enrico | ||||
Title | System Level Formal Verification via Distributed Multi-Core Hardware in the Loop Simulation | Type | Conference Article | ||
Year | 2014 | Publication | Proc. of the 22nd Euromicro International Conference on Parallel, Distributed and Network-Based Processing | Abbreviated Journal | Euromicro International Conference on Parallel, Distributed and Network-Based Processing |
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Publisher | IEEE Computer Society | Place of Publication | Editor | ||
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Notes | Approved | no | |||
Call Number | Sapienza @ melatti @ | Serial | 118 | ||
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Author | Alimguzhin, Vadim; Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico | ||||
Title | Automatic Control Software Synthesis for Quantized Discrete Time Hybrid Systems | Type | Conference Article | ||
Year | 2012 | Publication | Proceedings of the 51th IEEE Conference on Decision and Control, CDC 2012, December 10-13, 2012, Maui, HI, USA | Abbreviated Journal | |
Volume | Issue | Pages | 6120-6125 | ||
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Publisher | IEEE | Place of Publication | Editor | ||
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ISSN | ISBN | 978-1-4673-2065-8 | Medium | ||
Area | Expedition | Conference | |||
Notes | Techreport version can be found at http://arxiv.org/abs/1207.4098 | Approved | yes | ||
Call Number | Sapienza @ mari @ cdc12 | Serial | 96 | ||
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Author | Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico | ||||
Title | Linear Constraints and Guarded Predicates as a Modeling Language for Discrete Time Hybrid Systems | Type | Journal Article | ||
Year | 2013 | Publication | International Journal on Advances in Software | Abbreviated Journal | Intern. Journal on Advances in SW |
Volume | vol. 6, nr 1&2 | Issue | Pages | 155-169 | |
Keywords | Model-based software design; Linear predicates; Hybrid systems | ||||
Abstract | Model based design is particularly appealing in
software based control systems (e.g., embedded software) design, since in such a case system level specifications are much easier to define than the control software behavior itself. In turn, model based design of embedded systems requires modeling both continuous subsystems (typically, the plant) as well as discrete subsystems (the controller). This is typically done using hybrid systems. Mixed Integer Linear Programming (MILP) based abstraction techniques have been successfully applied to automatically synthesize correct-by-construction control software for discrete time linear hybrid systems, where plant dynamics is modeled as a linear predicate over state, input, and next state variables. Unfortunately, MILP solvers require such linear predicates to be conjunctions of linear constraints, which is not a natural way of modeling hybrid systems. In this paper we show that, under the hypothesis that each variable ranges over a bounded interval, any linear predicate built upon conjunction and disjunction of linear constraints can be automatically translated into an equivalent conjunctive predicate. Since variable bounds play a key role in this translation, our algorithm includes a procedure to compute all implicit variable bounds of the given linear predicate. Furthermore, we show that a particular form of linear predicates, namely guarded predicates, are a natural and powerful language to succinctly model discrete time linear hybrid systems dynamics. Finally, we experimentally show the feasibility of our approach on an important and challenging case study taken from the literature, namely the multi-input Buck DC-DC Converter. As an example, the guarded predicate that models (with 57 constraints) a 6-inputs Buck DC-DC Converter is translated in a conjunctive predicate (with 102 linear constraints) in about 40 minutes. |
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Publisher | IARIA | Place of Publication | Editor | Luigi Lavazza | |
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Series Volume | Series Issue | Edition | |||
ISSN | 1942-2628 | ISBN | Medium | ||
Area | Expedition | Conference | |||
Notes | Approved | yes | |||
Call Number | Sapienza @ melatti @ | Serial | 115 | ||
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Author | Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico | ||||
Title | Synthesizing Control Software from Boolean Relations | Type | Journal Article | ||
Year | 2012 | Publication | International Journal on Advances in Software | Abbreviated Journal | Intern. Journal on Advances in SW |
Volume | vol. 5, nr 3&4 | Issue | Pages | 212-223 | |
Keywords | Control Software Synthesis; Embedded Systems; Model Checking | ||||
Abstract | Many software as well digital hardware automatic
synthesis methods define the set of implementations meeting the given system specifications with a boolean relation K. In such a context a fundamental step in the software (hardware) synthesis process is finding effective solutions to the functional equation defined by K. This entails finding a (set of) boolean function(s) F (typically represented using OBDDs, Ordered Binary Decision Diagrams) such that: 1) for all x for which K is satisfiable, K(x, F(x)) = 1 holds; 2) the implementation of F is efficient with respect to given implementation parameters such as code size or execution time. While this problem has been widely studied in digital hardware synthesis, little has been done in a software synthesis context. Unfortunately, the approaches developed for hardware synthesis cannot be directly used in a software context. This motivates investigation of effective methods to solve the above problem when F has to be implemented with software. In this paper, we present an algorithm that, from an OBDD representation for K, generates a C code implementation for F that has the same size as the OBDD for F and a worst case execution time linear in nr, being n = |x| the number of input arguments for functions in F and r the number of functions in F. Moreover, a formal proof of the proposed algorithm correctness is also shown. Finally, we present experimental results showing effectiveness of the proposed algorithm. |
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Publisher | IARIA | Place of Publication | Editor | Luigi Lavazza | |
Language | Summary Language | Original Title | |||
Series Editor | Series Title | Abbreviated Series Title | |||
Series Volume | Series Issue | Edition | |||
ISSN | 1942-2628 | ISBN | Medium | ||
Area | Expedition | Conference | |||
Notes | Approved | yes | |||
Call Number | Sapienza @ melatti @ | Serial | 108 | ||
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Author | Barbanera, Franco; Dezani-Ciancaglini, Mariangiola; Salvo, Ivano; Sassone, Vladimiro | ||||
Title | A Type Inference Algorithm for Secure Ambients | Type | Journal Article | ||
Year | 2002 | Publication | Electronic Notes in Theoretical Computer Science | Abbreviated Journal | |
Volume | 62 | Issue | Pages | 83-101 | |
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Abstract | We consider a type discipline for the Ambient Calculus that associates ambients with security levels and constrains them to be traversed by or opened in ambients of higher security clearance only. We present a bottom-up algorithm that, given an untyped process P, computes a minimal set of constraints on security levels such that all actions during runs of P are performed without violating the security level priorities. Such an algorithm appears to be a prerequisite to use type systems to ensure security properties in the web scenario. | ||||
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Publisher | Elsevier | Place of Publication | Editor | ||
Language | Summary Language | Original Title | |||
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Notes | TOSCA 2001, Theory of Concurrency, Higher Order Languages and Types | Approved | yes | ||
Call Number | Sapienza @ mari @ Barbanera-Dezani-Salvo-Sassone:01 | Serial | 73 | ||
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Author | Alimguzhin, Vadim; Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico | ||||
Title | Automatic Control Software Synthesis for Quantized Discrete Time Hybrid Systems | Type | Report | ||
Year | 2012 | Publication | Abbreviated Journal | ||
Volume | abs/1207.4098 | Issue | Pages | ||
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Abstract | Many Embedded Systems are indeed Software Based Control Systems, that is control systems whose controller consists of control software running on a microcontroller device. This motivates investigation on Formal Model Based Design approaches for automatic synthesis of embedded systems control software. This paper addresses control software synthesis for discrete time nonlinear systems. We present a methodology to overapproximate the dynamics of a discrete time nonlinear hybrid system H by means of a discrete time linear hybrid system L(H), in such a way that controllers for L(H) are guaranteed to be controllers for H. We present experimental results on the inverted pendulum, a challenging and meaningful benchmark in nonlinear Hybrid Systems control. | ||||
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Publisher | CoRR, Technical Report | Place of Publication | Editor | ||
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Notes | Approved | yes | |||
Call Number | Sapienza @ mari @ | Serial | 103 | ||
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Author | Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico | ||||
Title | Quantized Feedback Control Software Synthesis from System Level Formal Specifications for Buck DC/DC Converters | Type | Report | ||
Year | 2011 | Publication | Abbreviated Journal | ||
Volume | abs/1105.5640 | Issue | Pages | ||
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Abstract | Many Embedded Systems are indeed Software Based Control Systems (SBCSs), that is control systems whose controller consists of control software running on a microcontroller device. This motivates investigation on Formal Model Based Design approaches for automatic synthesis of SBCS control software. In previous works we presented an algorithm, along with a tool QKS implementing it, that from a formal model (as a Discrete Time Linear Hybrid System, DTLHS) of the controlled system (plant), implementation specifications (that is, number of bits in the Analog-to-Digital, AD, conversion) and System Level Formal Specifications (that is, safety and liveness requirements for the closed loop system) returns correct-by-construction control software that has a Worst Case Execution Time (WCET) linear in the number of AD bits and meets the given specifications. In this technical report we present full experimental results on using it to synthesize control software for two versions of buck DC-DC converters (single-input and multi-input), a widely used mixed-mode analog circuit. | ||||
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Publisher | CoRR, Technical Report | Place of Publication | Editor | ||
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Notes | Approved | yes | |||
Call Number | Sapienza @ mari @ | Serial | 106 | ||
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Author | Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico | ||||
Title | From Boolean Functional Equations to Control Software | Type | Report | ||
Year | 2011 | Publication | Abbreviated Journal | ||
Volume | abs/1106.0468 | Issue | Pages | ||
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Abstract | Many software as well digital hardware automatic synthesis methods define the set of implementations meeting the given system specifications with a boolean relation K. In such a context a fundamental step in the software (hardware) synthesis process is finding effective solutions to the functional equation defined by K. This entails finding a (set of) boolean function(s) F (typically represented using OBDDs, Ordered Binary Decision Diagrams) such that: 1) for all x for which K is satisfiable, K(x, F(x)) = 1 holds; 2) the implementation of F is efficient with respect to given implementation parameters such as code size or execution time. While this problem has been widely studied in digital hardware synthesis, little has been done in a software synthesis context. Unfortunately the approaches developed for hardware synthesis cannot be directly used in a software context. This motivates investigation of effective methods to solve the above problem when F has to be implemented with software. In this paper we present an algorithm that, from an OBDD representation for K, generates a C code implementation for F that has the same size as the OBDD for F and a WCET (Worst Case Execution Time) at most O(nr), being n = |x| the number of arguments of functions in F and r the number of functions in F. | ||||
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Publisher | CoRR, Technical Report | Place of Publication | Editor | ||
Language | Summary Language | Original Title | |||
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Notes | Approved | yes | |||
Call Number | Sapienza @ mari @ | Serial | 105 | ||
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