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Author | Alimguzhin, V.; Mari, F.; Melatti, I.; Salvo, I.; Tronci, E. | ||||
Title | Linearising Discrete Time Hybrid Systems | Type | Journal Article | ||
Year | 2017 | Publication | IEEE Transactions on Automatic Control | Abbreviated Journal | |
Volume | 62 | Issue | 10 | Pages | 5357-5364 |
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Abstract | Model Based Design approaches for embedded systems aim at generating correct-by-construction control software, guaranteeing that the closed loop system (controller and plant) meets given system level formal specifications. This technical note addresses control synthesis for safety and reachability properties of possibly non-linear discrete time hybrid systems. By means of syntactical transformations that require non-linear terms to be Lipschitz continuous functions, we over-approximate non-linear dynamics with a linear system whose controllers are guaranteed to be controllers of the original system. We evaluate performance of our approach on meaningful control synthesis benchmarks, also comparing it to a state-of-the-art tool. | ||||
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ISSN | 0018-9286 | ISBN | Medium | ||
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Notes | Approved | no | |||
Call Number | Sapienza @ mari @ ref7902199 | Serial | 164 | ||
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Author | Barbanera, Franco; Dezani-Ciancaglini, Mariangiola; Salvo, Ivano; Sassone, Vladimiro | ||||
Title | A Type Inference Algorithm for Secure Ambients | Type | Journal Article | ||
Year | 2002 | Publication | Electronic Notes in Theoretical Computer Science | Abbreviated Journal | |
Volume | 62 | Issue | Pages | 83-101 | |
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Abstract | We consider a type discipline for the Ambient Calculus that associates ambients with security levels and constrains them to be traversed by or opened in ambients of higher security clearance only. We present a bottom-up algorithm that, given an untyped process P, computes a minimal set of constraints on security levels such that all actions during runs of P are performed without violating the security level priorities. Such an algorithm appears to be a prerequisite to use type systems to ensure security properties in the web scenario. | ||||
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Publisher | Elsevier | Place of Publication | Editor | ||
Language | Summary Language | Original Title | |||
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Notes | TOSCA 2001, Theory of Concurrency, Higher Order Languages and Types | Approved | yes | ||
Call Number | Sapienza @ mari @ Barbanera-Dezani-Salvo-Sassone:01 | Serial | 73 | ||
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Author | Della Penna, Giuseppe; Intrigila, Benedetto; Tronci, Enrico; Venturini Zilli, Marisa | ||||
Title | Synchronized Regular Expressions | Type | Journal Article | ||
Year | 2002 | Publication | Electr. Notes Theor. Comput. Sci. | Abbreviated Journal | |
Volume | 62 | Issue | Pages | 195-210 | |
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Abstract | Text manipulation is one of the most common tasks for everyone using a computer. The increasing number of textual information in electronic format that every computer user collects everyday stresses the need of more powerful tools to interact with texts. Indeed, much work has been done to provide nonprogramming tools that can be useful for the most common text manipulation issues. Regular Expressions (RE), introduced by Kleene, are well–known in the formal language theory. RE received several extensions, depending on the application of interest. In almost all the implementations of RE search algorithms (e.g. the egrep [A] UNIX command, or the Perl [17] language pattern matching constructs) we find backreferences (as defind in [1]), i.e. expressions that make reference to the string matched by a previous subexpression. Generally speaking, it seems that all the kinds of synchronizations between subexpressions in a RE can be very useful when interacting with texts. Therefore, we introduce the Synchronized Regular Expressions (SRE) as a derivation of the Regular Expressions. We use SRE to present a formal study of the already known backreferences extension, and of a new extension proposed by us, which we call the synchronized exponents. Moreover, since we are talking about formalisms that should have a practical utility and can be used in the real world, we have the problem of how to present SRE to the final users. Therefore, in this paper we also propose a user–friendly syntax for SRE to be used in implementations of SRE–powered search algorithms. | ||||
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Notes | TOSCA 2001, Theory of Concurrency, Higher Order Languages and Types | Approved | yes | ||
Call Number | Sapienza @ mari @ entcs02 | Serial | 46 | ||
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Author | Mancini, T.; Mari, F.; Massini, A.; Melatti, I.; Tronci, E. | ||||
Title | Anytime system level verification via parallel random exhaustive hardware in the loop simulation | Type | Journal Article | ||
Year | 2016 | Publication | Microprocessors and Microsystems | Abbreviated Journal | |
Volume | 41 | Issue | Pages | 12-28 | |
Keywords | Model Checking of Hybrid Systems; Model checking driven simulation; Hardware in the loop simulation | ||||
Abstract | Abstract System level verification of cyber-physical systems has the goal of verifying that the whole (i.e., software + hardware) system meets the given specifications. Model checkers for hybrid systems cannot handle system level verification of actual systems. Thus, Hardware In the Loop Simulation (HILS) is currently the main workhorse for system level verification. By using model checking driven exhaustive HILS, System Level Formal Verification (SLFV) can be effectively carried out for actual systems. We present a parallel random exhaustive HILS based model checker for hybrid systems that, by simulating all operational scenarios exactly once in a uniform random order, is able to provide, at any time during the verification process, an upper bound to the probability that the System Under Verification exhibits an error in a yet-to-be-simulated scenario (Omission Probability). We show effectiveness of the proposed approach by presenting experimental results on SLFV of the Inverted Pendulum on a Cart and the Fuel Control System examples in the Simulink distribution. To the best of our knowledge, no previously published model checker can exhaustively verify hybrid systems of such a size and provide at any time an upper bound to the Omission Probability. | ||||
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Series Volume | Series Issue | Edition | |||
ISSN | 0141-9331 | ISBN | Medium | ||
Area | Expedition | Conference | |||
Notes | Approved | no | |||
Call Number | MCLab @ davi @ Mancini201612 | Serial | 155 | ||
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Author | Della Penna, Giuseppe; Intrigila, Benedetto; Tronci, Enrico; Venturini Zilli, Marisa | ||||
Title | Synchronized regular expressions | Type | Journal Article | ||
Year | 2003 | Publication | Acta Inf. | Abbreviated Journal | |
Volume | 39 | Issue | 1 | Pages | 31-70 |
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Abstract | Text manipulation is one of the most common tasks for everyone using a computer. The increasing number of textual information in electronic format that every computer user collects everyday also increases the need of more powerful tools to interact with texts. Indeed, much work has been done to provide simple and versatile tools that can be useful for the most common text manipulation tasks. Regular Expressions (RE), introduced by Kleene, are well known in the formal language theory. RE have been extended in various ways, depending on the application of interest. In almost all the implementations of RE search algorithms (e.g. the egrep [15] UNIX command, or the Perl [20] language pattern matching constructs) we find backreferences, i.e. expressions that make reference to the string matched by a previous subexpression. Generally speaking, it seems that all kinds of synchronizations between subexpressions in a RE can be very useful when interacting with texts. In this paper we introduce the Synchronized Regular Expressions (SRE) as an extension of the Regular Expressions. We use SRE to present a formal study of the already known backreferences extension, and of a new extension proposed by us, which we call the synchronized exponents. Moreover, since we are dealing with formalisms that should have a practical utility and be used in real applications, we have the problem of how to present SRE to the final users. Therefore, in this paper we also propose a user-friendly syntax for SRE to be used in implementations of SRE-powered search algorithms. | ||||
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Area | Expedition | Conference | |||
Notes | Approved | yes | |||
Call Number | Sapienza @ mari @ actainf03 | Serial | 39 | ||
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Author | Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico | ||||
Title | Model Based Synthesis of Control Software from System Level Formal Specifications | Type | Journal Article | ||
Year | 2014 | Publication | ACM TRANSACTIONS ON SOFTWARE ENGINEERING AND METHODOLOGY | Abbreviated Journal | ACM TRANSACTIONS ON SOFTWARE ENGINEERING AND METHODOLOGY |
Volume | 23 | Issue | 1 | Pages | Article 6 |
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Publisher | ACM | Place of Publication | Editor | ||
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Series Volume | Series Issue | Edition | |||
ISSN | 1049-331X | ISBN | Medium | ||
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Notes | Approved | no | |||
Call Number | Sapienza @ melatti @ | Serial | 110 | ||
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Author | Della Penna, Giuseppe; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico; Venturini Zilli, Marisa | ||||
Title | Finite horizon analysis of Markov Chains with the Mur$\varphi$ verifier | Type | Journal Article | ||
Year | 2006 | Publication | Int. J. Softw. Tools Technol. Transf. | Abbreviated Journal | |
Volume | 8 | Issue | 4 | Pages | 397-409 |
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Abstract | In this paper we present an explicit disk-based verification algorithm for Probabilistic Systems defining discrete time/finite state Markov Chains. Given a Markov Chain and an integer k (horizon), our algorithm checks whether the probability of reaching an error state in at most k steps is below a given threshold. We present an implementation of our algorithm within a suitable extension of the Mur$\varphi$ verifier. We call the resulting probabilistic model checker FHP-Mur$\varphi$ (Finite Horizon Probabilistic Mur$\varphi$). We present experimental results comparing FHP-Mur$\varphi$ with (a finite horizon subset of) PRISM, a state-of-the-art symbolic model checker for Markov Chains. Our experimental results show that FHP-Mur$\varphi$ can handle systems that are out of reach for PRISM, namely those involving arithmetic operations on the state variables (e.g. hybrid systems). | ||||
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Publisher | Springer-Verlag | Place of Publication | Berlin, Heidelberg | Editor | |
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ISSN | 1433-2779 | ISBN | Medium | ||
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Notes | Approved | yes | |||
Call Number | Sapienza @ mari @ Dimtz06 | Serial | 78 | ||
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Author | Della Penna, Giuseppe; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico; Venturini Zilli, Marisa | ||||
Title | Exploiting Transition Locality in Automatic Verification of Finite State Concurrent Systems | Type | Journal Article | ||
Year | 2004 | Publication | Sttt | Abbreviated Journal | |
Volume | 6 | Issue | 4 | Pages | 320-341 |
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Abstract | In this paper we show that statistical properties of the transition graph of a system to be verified can be exploited to improve memory or time performances of verification algorithms. We show experimentally that protocols exhibit transition locality. That is, with respect to levels of a breadth-first state space exploration, state transitions tend to be between states belonging to close levels of the transition graph. We support our claim by measuring transition locality for the set of protocols included in the Mur$\varphi$ verifier distribution. We present a cache-based verification algorithm that exploits transition locality to decrease memory usage and a disk-based verification algorithm that exploits transition locality to decrease disk read accesses, thus reducing the time overhead due to disk usage. Both algorithms have been implemented within the Mur$\varphi$ verifier. Our experimental results show that our cache-based algorithm can typically save more than 40% of memory with an average time penalty of about 50% when using (Mur$\varphi$) bit compression and 100% when using bit compression and hash compaction, whereas our disk-based verification algorithm is typically more than ten times faster than a previously proposed disk-based verification algorithm and, even when using 10% of the memory needed to complete verification, it is only between 40 and 530% (300% on average) slower than (RAM) Mur$\varphi$ with enough memory to complete the verification task at hand. Using just 300 MB of memory our disk-based Mur$\varphi$ was able to complete verification of a protocol with about $10^9$ reachable states. This would require more than 5 GB of memory using standard Mur$\varphi$. | ||||
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Notes | Approved | yes | |||
Call Number | Sapienza @ mari @ DIMTZ04j | Serial | 91 | ||
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Author | Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico | ||||
Title | Linear Constraints and Guarded Predicates as a Modeling Language for Discrete Time Hybrid Systems | Type | Journal Article | ||
Year | 2013 | Publication | International Journal on Advances in Software | Abbreviated Journal | Intern. Journal on Advances in SW |
Volume | vol. 6, nr 1&2 | Issue | Pages | 155-169 | |
Keywords | Model-based software design; Linear predicates; Hybrid systems | ||||
Abstract | Model based design is particularly appealing in
software based control systems (e.g., embedded software) design, since in such a case system level specifications are much easier to define than the control software behavior itself. In turn, model based design of embedded systems requires modeling both continuous subsystems (typically, the plant) as well as discrete subsystems (the controller). This is typically done using hybrid systems. Mixed Integer Linear Programming (MILP) based abstraction techniques have been successfully applied to automatically synthesize correct-by-construction control software for discrete time linear hybrid systems, where plant dynamics is modeled as a linear predicate over state, input, and next state variables. Unfortunately, MILP solvers require such linear predicates to be conjunctions of linear constraints, which is not a natural way of modeling hybrid systems. In this paper we show that, under the hypothesis that each variable ranges over a bounded interval, any linear predicate built upon conjunction and disjunction of linear constraints can be automatically translated into an equivalent conjunctive predicate. Since variable bounds play a key role in this translation, our algorithm includes a procedure to compute all implicit variable bounds of the given linear predicate. Furthermore, we show that a particular form of linear predicates, namely guarded predicates, are a natural and powerful language to succinctly model discrete time linear hybrid systems dynamics. Finally, we experimentally show the feasibility of our approach on an important and challenging case study taken from the literature, namely the multi-input Buck DC-DC Converter. As an example, the guarded predicate that models (with 57 constraints) a 6-inputs Buck DC-DC Converter is translated in a conjunctive predicate (with 102 linear constraints) in about 40 minutes. |
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Publisher | IARIA | Place of Publication | Editor | Luigi Lavazza | |
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Series Volume | Series Issue | Edition | |||
ISSN | 1942-2628 | ISBN | Medium | ||
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Notes | Approved | yes | |||
Call Number | Sapienza @ melatti @ | Serial | 115 | ||
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Author | Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico | ||||
Title | Synthesizing Control Software from Boolean Relations | Type | Journal Article | ||
Year | 2012 | Publication | International Journal on Advances in Software | Abbreviated Journal | Intern. Journal on Advances in SW |
Volume | vol. 5, nr 3&4 | Issue | Pages | 212-223 | |
Keywords | Control Software Synthesis; Embedded Systems; Model Checking | ||||
Abstract | Many software as well digital hardware automatic
synthesis methods define the set of implementations meeting the given system specifications with a boolean relation K. In such a context a fundamental step in the software (hardware) synthesis process is finding effective solutions to the functional equation defined by K. This entails finding a (set of) boolean function(s) F (typically represented using OBDDs, Ordered Binary Decision Diagrams) such that: 1) for all x for which K is satisfiable, K(x, F(x)) = 1 holds; 2) the implementation of F is efficient with respect to given implementation parameters such as code size or execution time. While this problem has been widely studied in digital hardware synthesis, little has been done in a software synthesis context. Unfortunately, the approaches developed for hardware synthesis cannot be directly used in a software context. This motivates investigation of effective methods to solve the above problem when F has to be implemented with software. In this paper, we present an algorithm that, from an OBDD representation for K, generates a C code implementation for F that has the same size as the OBDD for F and a worst case execution time linear in nr, being n = |x| the number of input arguments for functions in F and r the number of functions in F. Moreover, a formal proof of the proposed algorithm correctness is also shown. Finally, we present experimental results showing effectiveness of the proposed algorithm. |
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Publisher | IARIA | Place of Publication | Editor | Luigi Lavazza | |
Language | Summary Language | Original Title | |||
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Series Volume | Series Issue | Edition | |||
ISSN | 1942-2628 | ISBN | Medium | ||
Area | Expedition | Conference | |||
Notes | Approved | yes | |||
Call Number | Sapienza @ melatti @ | Serial | 108 | ||
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