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Author Tronci, Enrico
Title Introductory Paper Type Journal Article
Year 2006 Publication Sttt Abbreviated Journal (up)
Volume 8 Issue 4-5 Pages 355-358
Keywords
Abstract In today’s competitive market designing of digital systems (hardware as well as software) faces tremendous challenges. In fact, notwithstanding an ever decreasing project budget, time to market and product lifetime, designers are faced with an ever increasing system complexity and customer expected quality. The above situation calls for better and better formal verification techniques at all steps of the design flow. This special issue is devoted to publishing revised versions of contributions first presented at the 12th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME) held 21–24 October 2003 in L’Aquila, Italy. Authors of well regarded papers from CHARME’03 were invited to submit to this special issue. All papers included here have been suitably extended and have undergone an independent round of reviewing.
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Call Number Sapienza @ mari @ sttt06 Serial 30
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Author Della Penna, Giuseppe; Magazzeni, Daniele; Tofani, Alberto; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico
Title Automated Generation Of Optimal Controllers Through Model Checking Techniques Type Book Chapter
Year 2008 Publication Informatics in Control Automation and Robotics. Selected Papers from ICINCO 2006 Abbreviated Journal (up)
Volume Issue Pages 107-119
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Publisher Springer Place of Publication Editor
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Call Number Sapienza @ mari @ Dmtmt08 Serial 26
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Author Bartolini, Novella; Tronci, Enrico
Title On Optimizing Service Availability of an Internet Based Architecture for Infrastructure Protection Type Conference Article
Year 2006 Publication Cnip Abbreviated Journal (up)
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Call Number Sapienza @ mari @ Bt06 Serial 28
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Author Cecconi, Michele; Tronci, Enrico
Title Requirements Formalization and Validation for a Telecommunication Equipment Protection Switcher Type Conference Article
Year 2000 Publication Hase Abbreviated Journal (up)
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Publisher IEEE Computer Society Place of Publication Editor
Language Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
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ISSN 0-7695-0927-4 ISBN Medium
Area Expedition Conference
Notes Approved yes
Call Number Sapienza @ mari @ CeTro00 Serial 29
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Author Cesta, Amedeo; Finzi, Alberto; Fratini, Simone; Orlandini, Andrea; Tronci, Enrico
Title Merging Planning, Scheduling & Verification – A Preliminary Analysis Type Conference Article
Year 2008 Publication In Proc. of 10th ESA Workshop on Advanced Space Technologies for Robotics and Automation (ASTRA) Abbreviated Journal (up)
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Call Number Sapienza @ mari @ Astra08 Serial 24
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Author Cesta, Amedeo; Finzi, Alberto; Fratini, Simone; Orlandini, Andrea; Tronci, Enrico
Title Validation and Verification Issues in a Timeline-based Planning System Type Conference Article
Year 2008 Publication In E-Proc. of ICAPS Workshop on Knowledge Engineering for Planning and Scheduling Abbreviated Journal (up)
Volume Issue Pages
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Abstract One of the key points to take into account to foster effective introduction of AI planning and scheduling systems in real world is to develop end user trust in the related technologies. Automated planning and scheduling systems often brings solutions to the users which are neither “obvious†nor immediately acceptable for them. This is due to the ability of these tools to take into account quite an amount of temporal and causal constraints and to employ resolution processes often designed to optimize the solution with respect to non trivial evaluation functions. To increase technology trust, the study of tools for verifying and validating plans and schedules produced by AI systems might be instrumental. In general, validation and verification techniques represent a needed complementary technology in developing domain independent architectures for automated problem solving. This paper presents a preliminary report of the issues concerned with the use of two software tools for formal verification of finite state systems to the validation of the solutions produced by MrSPOCK, a recent effort for building a timeline based planning tool in an ESA project.
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Call Number Sapienza @ mari @ Keps08 Serial 25
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Author Cesta, Amedeo; Finzi, Alberto; Fratini, Simone; Orlandini, Andrea; Tronci, Enrico
Title Verifying Flexible Timeline-based Plans Type Conference Article
Year 2009 Publication E-Proc. of ICAPS Workshop on Validation and Verification of Planning and Scheduling Systems Abbreviated Journal (up)
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Abstract The synthesis of flexible temporal plans has demonstrated wide applications possibilities in heterogeneous domains. We are currently studying the connection between plan generation and execution from the particular perspective of verifying a flexible plan before actual execution. This paper explores how a model-checking verification tool, based on UPPAAL-TIGA, is suitable for verifying flexible temporal plans. We first describe the formal model, the formalism, and the verification method. Furthermore we discuss our own approach and some preliminary empirical results using a real-world case study.
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Call Number Sapienza @ mari @ Vvps09 Serial 23
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Author Gorrieri, Roberto; Lanotte, Ruggero; Maggiolo-Schettini, Andrea; Martinelli, Fabio; Tini, Simone; Tronci, Enrico
Title Automated analysis of timed security: a case study on web privacy Type Journal Article
Year 2004 Publication International Journal of Information Security Abbreviated Journal (up)
Volume 2 Issue 3-4 Pages 168-186
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Abstract This paper presents a case study on an automated analysis of real-time security models. The case study on a web system (originally proposed by Felten and Schneider) is presented that shows a timing attack on the privacy of browser users. Three different approaches are followed: LH-Timed Automata (analyzed using the model checker HyTech), finite-state automata (analyzed using the model checker NuSMV), and process algebras (analyzed using the model checker CWB-NC). A comparative analysis of these three approaches is given.
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Call Number Sapienza @ mari @ ijis04 Serial 33
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Author Lanotte, Ruggero; Maggiolo-Schettini, Andrea; Tini, Simone; Troina, Angelo; Tronci, Enrico
Title Automatic Covert Channel Analysis of a Multilevel Secure Component Type Conference Article
Year 2004 Publication Information and Communications Security, 6th International Conference, ICICS 2004, Malaga, Spain, October 27-29, 2004, Proceedings Abbreviated Journal (up)
Volume Issue Pages 249-261
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Abstract The NRL Pump protocol defines a multilevel secure component whose goal is to minimize leaks of information from high level systems to lower level systems, without degrading average time performances. We define a probabilistic model for the NRL Pump and show how a probabilistic model checker (FHP-mur$\varphi$) can be used to estimate the capacity of a probabilistic covert channel in the NRL Pump. We are able to compute the probability of a security violation as a function of time for various configurations of the system parameters (e.g. buffer sizes, moving average size, etc). Because of the model complexity, our results cannot be obtained using an analytical approach and, because of the low probabilities involved, it can be hard to obtain them using a simulator.
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Publisher Springer Place of Publication Editor Lopez, J.; Qing, S.; Okamoto, E.
Language Summary Language Original Title
Series Editor Series Title Lecture Notes in Computer Science Abbreviated Series Title
Series Volume 3269 Series Issue Edition
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Call Number Sapienza @ mari @ icics04 Serial 34
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Author Lanotte, Ruggero; Maggiolo-Schettini, Andrea; Tini, Simone; Troina, Angelo; Tronci, Enrico
Title Automatic Analysis of the NRL Pump Type Journal Article
Year 2004 Publication Electr. Notes Theor. Comput. Sci. Abbreviated Journal (up)
Volume 99 Issue Pages 245-266
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Abstract We define a probabilistic model for the NRL Pump and using FHP-mur$\varphi$ show experimentally that there exists a probabilistic covert channel whose capacity depends on various NRL Pump parameters (e.g. buffer size, number of samples in the moving average, etc).
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Call Number Sapienza @ mari @ entcs04 Serial 36
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