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Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Title |
From Boolean Relations to Control Software |
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Conference Article |
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2011 |
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Proceedings of ICSEA 2011, The Sixth International Conference on Software Engineering Advances |
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528-533 |
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Many software as well digital hardware automatic synthesis methods define the set of implementations meeting the given system specifications with a boolean relation K. In such a context a fundamental step in the software (hardware) synthesis process is finding effective solutions to the functional equation defined by K. This entails finding a (set of) boolean function(s) F (typically represented using OBDDs, Ordered Binary Decision Diagrams) such that: 1) for all x for which K is satisfiable, K(x, F(x)) = 1 holds; 2) the implementation of F is efficient with respect to given implementation parameters such as code size or execution time. While this problem has been widely studied in digital hardware synthesis, little has been done in a software synthesis context. Unfortunately the approaches developed for hardware synthesis cannot be directly used in a software context. This motivates investigation of effective methods to solve the above problem when F has to be implemented with software. In this paper we present an algorithm that, from an OBDD representation for K, generates a C code implementation for F that has the same size as the OBDD for F and a WCET (Worst Case Execution Time) linear in nr, being n = |x| the number of input arguments for functions in F and r the number of functions in F. |
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ThinkMind |
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978-1-61208-165-6 |
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yes |
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Sapienza @ mari @ icsea11 |
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14 |
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Author |
Lanotte, Ruggero; Maggiolo-Schettini, Andrea; Tini, Simone; Troina, Angelo; Tronci, Enrico |
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Title |
Automatic Covert Channel Analysis of a Multilevel Secure Component |
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Conference Article |
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2004 |
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Information and Communications Security, 6th International Conference, ICICS 2004, Malaga, Spain, October 27-29, 2004, Proceedings |
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249-261 |
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The NRL Pump protocol defines a multilevel secure component whose goal is to minimize leaks of information from high level systems to lower level systems, without degrading average time performances. We define a probabilistic model for the NRL Pump and show how a probabilistic model checker (FHP-mur$\varphi$) can be used to estimate the capacity of a probabilistic covert channel in the NRL Pump. We are able to compute the probability of a security violation as a function of time for various configurations of the system parameters (e.g. buffer sizes, moving average size, etc). Because of the model complexity, our results cannot be obtained using an analytical approach and, because of the low probabilities involved, it can be hard to obtain them using a simulator. |
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Springer |
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Lopez, J.; Qing, S.; Okamoto, E. |
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Lecture Notes in Computer Science |
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3269 |
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yes |
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Sapienza @ mari @ icics04 |
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34 |
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Author |
Tronci, Enrico |
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Title |
Automatic Synthesis of Controllers from Formal Specifications |
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Conference Article |
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Year |
1998 |
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Proc of 2nd IEEE International Conference on Formal Engineering Methods (ICFEM) |
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134-143 |
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Many safety critical reactive systems are indeed embedded control systems. Usually a control system can be partitioned into two main subsystems: a controller and a plant. Roughly speaking: the controller observes the state of the plant and sends commands (stimulus) to the plant to achieve predefined goals. We show that when the plant can be modeled as a deterministic finite state system (FSS) it is possible to effectively use formal methods to automatically synthesize the program implementing the controller from the plant model and the given formal specifications for the closed loop system (plant+controller). This guarantees that the controller program is correct by construction. To the best of our knowledge there is no previously published effective algorithm to extract executable code for the controller from closed loop formal specifications. We show practical usefulness of our techniques by giving experimental results on their use to synthesize C programs implementing optimal controllers (OCs) for plants with more than 109 states. |
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Brisbane, Queensland, Australia |
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yes |
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Call Number |
Sapienza @ mari @ icfem98 |
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52 |
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Author |
Tronci, Enrico |
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Title |
Formally Modeling a Metal Processing Plant and its Closed Loop Specifications |
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Conference Article |
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Year |
1999 |
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4th IEEE International Symposium on High-Assurance Systems Engineering (HASE) |
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151 |
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We present a case study on automatic synthesis of control software from formal specifications for an industrial automation control system. Our aim is to compare the effectiveness (i.e. design effort and controller quality) of automatic controller synthesis from closed loop formal specifications with that of manual controller design followed by automatic verification. The system to be controlled (plant) models a metal processing facility near Karlsruhe. We succeeded in automatically generating C code implementing a (correct by construction) embedded controller for such a plant from closed loop formal specifications. Our experimental results show that for industrial automation control systems automatic synthesis is a viable and profitable (especially as far as design effort is concerned) alternative to manual design followed by automatic verification. |
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IEEE Computer Society |
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Washington, D.C, USA |
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0-7695-0418-3 |
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yes |
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Call Number |
Sapienza @ mari @ hase99 |
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50 |
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Author |
Dipoppa, G.; D'Alessandro, G.; Semprini, R.; Tronci, E. |
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Title |
Integrating Automatic Verification of Safety Requirements in Railway Interlocking System Design |
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Conference Article |
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Year |
2001 |
Publication |
High Assurance Systems Engineering, 2001. Sixth IEEE International Symposium on |
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209-219 |
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A railway interlocking system (RIS) is an embedded system (namely a supervisory control system) that ensures the safe, operation of the devices in a railway station. RIS is a safety critical system. We explore the possibility of integrating automatic formal verification methods in a given industry RIS design flow. The main obstructions to be overcome in our work are: selecting a formal verification tool that is efficient enough to solve the verification problems at hand; and devising a cost effective integration strategy for such tool. We were able to devise a successful integration strategy meeting the above constraints without requiring major modification in the pre-existent design flow nor retraining of personnel. We run verification experiments for a RIS designed for the Singapore Subway. The experiments show that the RIS design flow obtained from our integration strategy is able to automatically verify real life RIS designs. |
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IEEE Computer Society |
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Albuquerque, NM, USA |
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0-7695-1275-5 |
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yes |
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Sapienza @ mari @ hase01 |
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45 |
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Author |
Pugliese, Rosario; Tronci, Enrico |
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Title |
Automatic Verification of a Hydroelectric Power Plant |
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Conference Article |
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1996 |
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Third International Symposium of Formal Methods Europe (FME), Co-Sponsored by IFIP WG 14.3 |
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425-444 |
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We analyze the specification of a hydroelectric power plant by ENEL (the Italian Electric Company). Our goal is to show that for the specification of the plant (its control system in particular) some given properties hold. We were provided with an informal specification of the plant. From such informal specification we wrote a formal specification using the CCS/Meije process algebra formalism. We defined properties using μ-calculus. Automatic verification was carried out using model checking. This was done by translating our process algebra definitions (the model) and μ-calculus formulas into BDDs. In this paper we present the informal specification of the plant, its formal specification, some of the properties we verified and experimental results. |
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Springer |
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Oxford, UK |
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Gaudel, M.-C.; Woodcock, J. |
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Lecture Notes in Computer Science |
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Series Volume |
1051 |
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3-540-60973-3 |
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yes |
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Sapienza @ mari @ fme96 |
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53 |
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Author |
Della Penna, Giuseppe; Intrigila, Benedetto; Tronci, Enrico; Venturini Zilli, Marisa |
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Title |
Exploiting Transition Locality in the Disk Based Mur$\varphi$ Verifier |
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Conference Article |
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2002 |
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4th International Conference on Formal Methods in Computer-Aided Design (FMCAD) |
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202-219 |
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The main obstruction to automatic verification of Finite State Systems is the huge amount of memory required to complete the verification task (state explosion). This motivates research on distributed as well as disk based verification algorithms. In this paper we present a disk based Breadth First Explicit State Space Exploration algorithm as well as an implementation of it within the Mur$\varphi$ verifier. Our algorithm exploits transition locality (i.e. the statistical fact that most transitions lead to unvisited states or to recently visited states) to decrease disk read accesses thus reducing the time overhead due to disk usage. A disk based verification algorithm for Mur$\varphi$ has been already proposed in the literature. To measure the time speed up due to locality exploitation we compared our algorithm with such previously proposed algorithm. Our experimental results show that our disk based verification algorithm is typically more than 10 times faster than such previously proposed disk based verification algorithm. To measure the time overhead due to disk usage we compared our algorithm with RAM based verification using the (standard) Mur$\varphi$ verifier with enough memory to complete the verification task. Our experimental results show that even when using 1/10 of the RAM needed to complete verification, our disk based algorithm is only between 1.4 and 5.3 times (3 times on average) slower than (RAM) Mur$\varphi$ with enough RAM memory to complete the verification task at hand. Using our disk based Mur$\varphi$ we were able to complete verification of a protocol with about $10^9$ reachable states. This would require more than 5 gigabytes of RAM using RAM based Mur$\varphi$. |
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Springer |
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Portland, OR, USA |
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Aagaard, M.; O'Leary, J.W. |
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Lecture Notes in Computer Science |
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2517 |
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3-540-00116-6 |
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yes |
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Sapienza @ mari @ fmcad02 |
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41 |
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Author |
Fantechi, Alessandro; Gnesi, Stefania; Mazzanti, Franco; Pugliese, Rosario; Tronci, Enrico |
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A Symbolic Model Checker for ACTL |
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Conference Article |
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1998 |
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International Workshop on Current Trends in Applied Formal Method (FM-Trends) |
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228-242 |
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We present SAM, a symbolic model checker for ACTL, the action-based version of CTL. SAM relies on implicit representations of Labeled Transition Systems (LTSs), the semantic domain for ACTL formulae, and uses symbolic manipulation algorithms. SAM has been realized by translating (networks of) LTSs and, possibly recursive, ACTL formulae into BSP (Boolean Symbolic Programming), a programming language aiming at defining computations on boolean functions, and by using the BSP interpreter to carry out computations (i.e. verifications). |
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Springer |
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Boppard, Germany |
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Hutter, D.; Stephan, W.; Traverso, P.; Ullmann, M. |
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Lecture Notes in Computer Science |
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1641 |
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3-540-66462-9 |
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yes |
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Sapienza @ mari @ fm-trends98 |
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51 |
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Author |
Cesta, Amedeo; Fratini, Simone; Orlandini, Andrea; Finzi, Alberto; Tronci, Enrico |
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Title |
Flexible Plan Verification: Feasibility Results |
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Journal Article |
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2011 |
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Fundamenta Informaticae |
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107 |
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2 |
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111-137 |
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Sapienza @ mari @ fi11 |
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15 |
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Author |
Lanotte, Ruggero; Maggiolo-Schettini, Andrea; Tini, Simone; Troina, Angelo; Tronci, Enrico |
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Title |
Automatic Analysis of the NRL Pump |
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Journal Article |
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2004 |
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Electr. Notes Theor. Comput. Sci. |
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99 |
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245-266 |
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We define a probabilistic model for the NRL Pump and using FHP-mur$\varphi$ show experimentally that there exists a probabilistic covert channel whose capacity depends on various NRL Pump parameters (e.g. buffer size, number of samples in the moving average, etc). |
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Sapienza @ mari @ entcs04 |
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36 |
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