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Author |
Alimguzhin, Vadim; Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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On Model Based Synthesis of Embedded Control Software |
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Conference Article |
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2012 |
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Proceedings of the 12th International Conference on Embedded Software, EMSOFT 2012, part of the Eighth Embedded Systems Week, ESWeek 2012, Tampere, Finland, October 7-12, 2012 |
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227-236 |
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ACM |
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Ahmed Jerraya and Luca P. Carloni and Florence Maraninchi and John Regehr |
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978-1-4503-1425-1 |
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Techreport version can be found at arxiv.org |
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yes |
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Sapienza @ mari @ emsoft12 |
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97 |
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Author |
Della Penna, Giuseppe; Intrigila, Benedetto; Tronci, Enrico; Venturini Zilli, Marisa |
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Title |
Synchronized Regular Expressions |
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Journal Article |
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2002 |
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Electr. Notes Theor. Comput. Sci. |
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62 |
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195-210 |
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Text manipulation is one of the most common tasks for everyone using a computer. The increasing number of textual information in electronic format that every computer user collects everyday stresses the need of more powerful tools to interact with texts. Indeed, much work has been done to provide nonprogramming tools that can be useful for the most common text manipulation issues. Regular Expressions (RE), introduced by Kleene, are well–known in the formal language theory. RE received several extensions, depending on the application of interest. In almost all the implementations of RE search algorithms (e.g. the egrep [A] UNIX command, or the Perl [17] language pattern matching constructs) we find backreferences (as defind in [1]), i.e. expressions that make reference to the string matched by a previous subexpression. Generally speaking, it seems that all the kinds of synchronizations between subexpressions in a RE can be very useful when interacting with texts. Therefore, we introduce the Synchronized Regular Expressions (SRE) as a derivation of the Regular Expressions. We use SRE to present a formal study of the already known backreferences extension, and of a new extension proposed by us, which we call the synchronized exponents. Moreover, since we are talking about formalisms that should have a practical utility and can be used in the real world, we have the problem of how to present SRE to the final users. Therefore, in this paper we also propose a user–friendly syntax for SRE to be used in implementations of SRE–powered search algorithms. |
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TOSCA 2001, Theory of Concurrency, Higher Order Languages and Types |
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yes |
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Sapienza @ mari @ entcs02 |
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46 |
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Focardi, Riccardo; Gorrieri, Roberto; Lanotte, Ruggero; Maggiolo-Schettini, Andrea; Martinelli, Fabio; Tini, Simone; Tronci, Enrico |
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Title |
Formal Models of Timing Attacks on Web Privacy |
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2002 |
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Electronic Notes in Theoretical Computer Science |
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62 |
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229-243 |
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We model a timing attack on web privacy proposed by Felten and Schneider by using three different approaches: HL-Timed Automata, SMV model checker, and tSPA Process Algebra. Some comparative analysis on the three approaches is derived. |
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TOSCA 2001, Theory of Concurrency, Higher Order Languages and Types |
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yes |
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Sapienza @ mari @ entcs02a |
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47 |
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Lanotte, Ruggero; Maggiolo-Schettini, Andrea; Tini, Simone; Troina, Angelo; Tronci, Enrico |
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Title |
Automatic Analysis of the NRL Pump |
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Journal Article |
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2004 |
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Electr. Notes Theor. Comput. Sci. |
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99 |
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245-266 |
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We define a probabilistic model for the NRL Pump and using FHP-mur$\varphi$ show experimentally that there exists a probabilistic covert channel whose capacity depends on various NRL Pump parameters (e.g. buffer size, number of samples in the moving average, etc). |
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yes |
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Sapienza @ mari @ entcs04 |
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36 |
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Author |
Cesta, Amedeo; Fratini, Simone; Orlandini, Andrea; Finzi, Alberto; Tronci, Enrico |
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Title |
Flexible Plan Verification: Feasibility Results |
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Journal Article |
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2011 |
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Fundamenta Informaticae |
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107 |
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2 |
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111-137 |
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yes |
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Sapienza @ mari @ fi11 |
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15 |
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Author |
Fantechi, Alessandro; Gnesi, Stefania; Mazzanti, Franco; Pugliese, Rosario; Tronci, Enrico |
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Title |
A Symbolic Model Checker for ACTL |
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Conference Article |
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1998 |
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International Workshop on Current Trends in Applied Formal Method (FM-Trends) |
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228-242 |
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We present SAM, a symbolic model checker for ACTL, the action-based version of CTL. SAM relies on implicit representations of Labeled Transition Systems (LTSs), the semantic domain for ACTL formulae, and uses symbolic manipulation algorithms. SAM has been realized by translating (networks of) LTSs and, possibly recursive, ACTL formulae into BSP (Boolean Symbolic Programming), a programming language aiming at defining computations on boolean functions, and by using the BSP interpreter to carry out computations (i.e. verifications). |
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Springer |
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Boppard, Germany |
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Hutter, D.; Stephan, W.; Traverso, P.; Ullmann, M. |
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Lecture Notes in Computer Science |
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1641 |
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3-540-66462-9 |
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yes |
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Call Number |
Sapienza @ mari @ fm-trends98 |
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51 |
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Author |
Della Penna, Giuseppe; Intrigila, Benedetto; Tronci, Enrico; Venturini Zilli, Marisa |
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Title |
Exploiting Transition Locality in the Disk Based Mur$\varphi$ Verifier |
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Conference Article |
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2002 |
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4th International Conference on Formal Methods in Computer-Aided Design (FMCAD) |
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202-219 |
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The main obstruction to automatic verification of Finite State Systems is the huge amount of memory required to complete the verification task (state explosion). This motivates research on distributed as well as disk based verification algorithms. In this paper we present a disk based Breadth First Explicit State Space Exploration algorithm as well as an implementation of it within the Mur$\varphi$ verifier. Our algorithm exploits transition locality (i.e. the statistical fact that most transitions lead to unvisited states or to recently visited states) to decrease disk read accesses thus reducing the time overhead due to disk usage. A disk based verification algorithm for Mur$\varphi$ has been already proposed in the literature. To measure the time speed up due to locality exploitation we compared our algorithm with such previously proposed algorithm. Our experimental results show that our disk based verification algorithm is typically more than 10 times faster than such previously proposed disk based verification algorithm. To measure the time overhead due to disk usage we compared our algorithm with RAM based verification using the (standard) Mur$\varphi$ verifier with enough memory to complete the verification task. Our experimental results show that even when using 1/10 of the RAM needed to complete verification, our disk based algorithm is only between 1.4 and 5.3 times (3 times on average) slower than (RAM) Mur$\varphi$ with enough RAM memory to complete the verification task at hand. Using our disk based Mur$\varphi$ we were able to complete verification of a protocol with about $10^9$ reachable states. This would require more than 5 gigabytes of RAM using RAM based Mur$\varphi$. |
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Springer |
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Portland, OR, USA |
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Aagaard, M.; O'Leary, J.W. |
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Lecture Notes in Computer Science |
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2517 |
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3-540-00116-6 |
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yes |
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Sapienza @ mari @ fmcad02 |
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41 |
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Author |
Pugliese, Rosario; Tronci, Enrico |
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Title |
Automatic Verification of a Hydroelectric Power Plant |
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Conference Article |
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1996 |
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Third International Symposium of Formal Methods Europe (FME), Co-Sponsored by IFIP WG 14.3 |
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425-444 |
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We analyze the specification of a hydroelectric power plant by ENEL (the Italian Electric Company). Our goal is to show that for the specification of the plant (its control system in particular) some given properties hold. We were provided with an informal specification of the plant. From such informal specification we wrote a formal specification using the CCS/Meije process algebra formalism. We defined properties using μ-calculus. Automatic verification was carried out using model checking. This was done by translating our process algebra definitions (the model) and μ-calculus formulas into BDDs. In this paper we present the informal specification of the plant, its formal specification, some of the properties we verified and experimental results. |
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Springer |
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Oxford, UK |
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Gaudel, M.-C.; Woodcock, J. |
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Lecture Notes in Computer Science |
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1051 |
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3-540-60973-3 |
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yes |
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Sapienza @ mari @ fme96 |
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53 |
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Dipoppa, G.; D'Alessandro, G.; Semprini, R.; Tronci, E. |
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Title |
Integrating Automatic Verification of Safety Requirements in Railway Interlocking System Design |
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Conference Article |
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2001 |
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High Assurance Systems Engineering, 2001. Sixth IEEE International Symposium on |
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209-219 |
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A railway interlocking system (RIS) is an embedded system (namely a supervisory control system) that ensures the safe, operation of the devices in a railway station. RIS is a safety critical system. We explore the possibility of integrating automatic formal verification methods in a given industry RIS design flow. The main obstructions to be overcome in our work are: selecting a formal verification tool that is efficient enough to solve the verification problems at hand; and devising a cost effective integration strategy for such tool. We were able to devise a successful integration strategy meeting the above constraints without requiring major modification in the pre-existent design flow nor retraining of personnel. We run verification experiments for a RIS designed for the Singapore Subway. The experiments show that the RIS design flow obtained from our integration strategy is able to automatically verify real life RIS designs. |
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IEEE Computer Society |
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Albuquerque, NM, USA |
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0-7695-1275-5 |
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yes |
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Sapienza @ mari @ hase01 |
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45 |
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Tronci, Enrico |
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Title |
Formally Modeling a Metal Processing Plant and its Closed Loop Specifications |
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1999 |
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4th IEEE International Symposium on High-Assurance Systems Engineering (HASE) |
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151 |
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We present a case study on automatic synthesis of control software from formal specifications for an industrial automation control system. Our aim is to compare the effectiveness (i.e. design effort and controller quality) of automatic controller synthesis from closed loop formal specifications with that of manual controller design followed by automatic verification. The system to be controlled (plant) models a metal processing facility near Karlsruhe. We succeeded in automatically generating C code implementing a (correct by construction) embedded controller for such a plant from closed loop formal specifications. Our experimental results show that for industrial automation control systems automatic synthesis is a viable and profitable (especially as far as design effort is concerned) alternative to manual design followed by automatic verification. |
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IEEE Computer Society |
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Washington, D.C, USA |
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0-7695-0418-3 |
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yes |
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Sapienza @ mari @ hase99 |
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50 |
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