| Records |
| Author |
Bucciarelli, Antonio; Salvo, Ivano |
| Title |
Totality, Definability and Boolean Circuits |
Type |
Journal Article |
| Year |
1998 |
Publication |
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Abbreviated Journal |
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| Volume |
1443 |
Issue |
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Pages |
808-819 |
| Keywords |
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| Abstract |
In the type frame originating from the flat domain of boolean values, we single out elements which are hereditarily total. We show that these elements can be defined, up to total equivalence, by sequential programs. The elements of an equivalence class of the totality equivalence relation (totality class) can be seen as different algorithms for computing a given set-theoretic boolean function. We show that the bottom element of a totality class, which is sequential, corresponds to the most eager algorithm, and the top to the laziest one. Finally we suggest a link between size of totality classes and a well known measure of complexity of boolean functions, namely their sensitivity. |
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| Publisher |
Springer |
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Approved |
yes |
Call Number  |
Sapienza @ mari @ bucciarelli-salvo:98 |
Serial |
70 |
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| Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
| Title |
Synthesis of Quantized Feedback Control Software for Discrete Time Linear Hybrid Systems |
Type |
Conference Article |
| Year |
2010 |
Publication |
Computer Aided Verification |
Abbreviated Journal |
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| Volume |
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Issue |
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Pages |
180-195 |
| Keywords |
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| Abstract |
We present an algorithm that given a Discrete Time Linear Hybrid System returns a correct-by-construction software implementation K for a (near time optimal) robust quantized feedback controller for along with the set of states on which K is guaranteed to work correctly (controllable region). Furthermore, K has a Worst Case Execution Time linear in the number of bits of the quantization schema. |
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| Publisher |
Springer Berlin / Heidelberg |
Place of Publication |
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Editor |
Touili, T.; Cook, B.; Jackson, P. |
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Series Title |
Lecture Notes in Computer Science |
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| Series Volume |
6174 |
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Approved |
yes |
| Call Number |
Sapienza @ mari @ cav2010 |
Serial |
16 |
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| Author |
Alimguzhin, Vadim; Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
| Title |
Automatic Control Software Synthesis for Quantized Discrete Time Hybrid Systems |
Type |
Conference Article |
| Year |
2012 |
Publication |
Proceedings of the 51th IEEE Conference on Decision and Control, CDC 2012, December 10-13, 2012, Maui, HI, USA |
Abbreviated Journal |
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Issue |
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Pages |
6120-6125 |
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| Publisher |
IEEE |
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978-1-4673-2065-8 |
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| Notes |
Techreport version can be found at http://arxiv.org/abs/1207.4098 |
Approved |
yes |
| Call Number |
Sapienza @ mari @ cdc12 |
Serial |
96 |
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| Author |
Tronci, Enrico |
| Title |
Optimal Finite State Supervisory Control |
Type |
Conference Article |
| Year |
1996 |
Publication |
CDC '96: Proceedings of the 35th IEEE International Conference on Decision and Control |
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Supervisory Controllers are Discrete Event Dynamic Systems (DEDSs) forming the discrete core of a Hybrid Control System. We address the problem of automatic synthesis of Optimal Finite State Supervisory Controllers (OSCs). We show that Boolean First Order Logic (BFOL) and Binary Decision Diagrams (BDDs) are an effective methodological and practical framework for Optimal Finite State Supervisory Control. Using BFOL programs (i.e. systems of boolean functional equations) and BDDs we give a symbolic (i.e. BDD based) algorithm for automatic synthesis of OSCs. Our OSC synthesis algorithm can handle arbitrary sets of final states as well as plant transition relations containing loops and uncontrollable events (e.g. failures). We report on experimental results on the use of our OSC synthesis algorithm to synthesize a C program implementing a minimum fuel OSC for two autonomous vehicles moving on a 4 x 4 grid. |
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IEEE Computer Society |
Place of Publication |
Washington, DC, USA |
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Approved |
yes |
| Call Number |
Sapienza @ mari @ cdc96 |
Serial |
67 |
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| Author |
Tronci, Enrico |
| Title |
On Computing Optimal Controllers for Finite State Systems |
Type |
Conference Article |
| Year |
1997 |
Publication |
CDC '97: Proceedings of the 36th IEEE International Conference on Decision and Control |
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| Publisher |
IEEE Computer Society |
Place of Publication |
Washington, DC, USA |
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Approved |
yes |
| Call Number |
Sapienza @ mari @ cdc97 |
Serial |
66 |
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| Author |
Böhm, Corrado; Tronci, Enrico |
| Title |
X-separability and left-invertibility in the λ-calculus (extended abstract, invited paper) |
Type |
Conference Article |
| Year |
1987 |
Publication |
Proceedings of: Temi e prospettive della Logica e della Filosofia della Scienza contemporanea |
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Place of Publication |
Cesena - Italy |
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Approved |
yes |
| Call Number |
Sapienza @ mari @ cesena87 |
Serial |
64 |
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| Author |
Cecconi, Michele; Tronci, Enrico |
| Title |
Requirements Formalization and Validation for a Telecommunication Equipment Protection Switcher |
Type |
Conference Article |
| Year |
2000 |
Publication |
Hase |
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Issue |
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Pages |
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IEEE Computer Society |
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0-7695-0927-4 |
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Approved |
yes |
| Call Number |
Sapienza @ mari @ CeTro00 |
Serial |
29 |
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| Author |
Cesta, Amedeo; Finzi, Alberto; Fratini, Simone; Orlandini, Andrea; Tronci, Enrico |
| Title |
Flexible Timeline-Based Plan Verification |
Type |
Conference Article |
| Year |
2009 |
Publication |
KI 2009: Advances in Artificial Intelligence, 32nd Annual German Conference on AI, Paderborn, Germany, September 15-18, 2009. Proceedings |
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Pages |
49-56 |
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Springer |
Place of Publication |
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Editor |
Mertsching, Bärbel; Hund, M.; Aziz, M.Z. |
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Series Title |
Lecture Notes in Computer Science |
Abbreviated Series Title |
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| Series Volume |
5803 |
Series Issue |
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Edition |
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| ISSN |
978-3-642-04616-2 |
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| Notes |
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Approved |
yes |
| Call Number |
Sapienza @ mari @ Cffot09 |
Serial |
21 |
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| Author |
Cesta, Amedeo; Finzi, Alberto; Fratini, Simone; Orlandini, Andrea; Tronci, Enrico |
| Title |
Validation and verification issues in a timeline-based planning system |
Type |
Journal Article |
| Year |
2010 |
Publication |
The Knowledge Engineering Review |
Abbreviated Journal |
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| Volume |
25 |
Issue |
03 |
Pages |
299-318 |
| Keywords |
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| Abstract |
One of the key points to take into account to foster effective introduction of AI planning and scheduling systems in real world is to develop end user trust in the related technologies. Automated planning and scheduling systems often brings solutions to the users which are neither “obviousÃ¢â‚¬Âť nor immediately acceptable for them. This is due to the ability of these tools to take into account quite an amount of temporal and causal constraints and to employ resolution processes often designed to optimize the solution with respect to non trivial evaluation functions. To increase technology trust, the study of tools for verifying and validating plans and schedules produced by AI systems might be instrumental. In general, validation and verification techniques represent a needed complementary technology in developing domain independent architectures for automated problem solving. This paper presents a preliminary report of the issues concerned with the use of two software tools for formal verification of finite state systems to the validation of the solutions produced by MrSPOCK, a recent effort for building a timeline based planning tool in an ESA project. |
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Cambridge University Press |
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| Notes |
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Approved |
yes |
| Call Number |
Sapienza @ mari @ Cffot10 |
Serial |
18 |
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| Author |
Tronci, Enrico; Della Penna, Giuseppe; Intrigila, Benedetto; Venturini Zilli, Marisa |
| Title |
Exploiting Transition Locality in Automatic Verification |
Type |
Conference Article |
| Year |
2001 |
Publication |
11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME) |
Abbreviated Journal |
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| Volume |
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Issue |
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Pages |
259-274 |
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| Abstract |
In this paper we present an algorithm to contrast state explosion when using Explicit State Space Exploration to verify protocols. We show experimentally that protocols exhibit transition locality. We present a verification algorithm that exploits transition locality as well as an implementation of it within the Mur$\varphi$ verifier. Our algorithm is compatible with all Breadth First (BF) optimization techniques present in the Mur$\varphi$ verifier and it is by no means a substitute for any of them. In fact, since our algorithm trades space with time, it is typically most useful when one runs out of memory and has already used all other state reduction techniques present in the Mur$\varphi$ verifier. Our experimental results show that using our approach we can typically save more than 40% of RAM with an average time penalty of about 50% when using (Mur$\varphi$) bit compression and 100% when using bit compression and hash compaction. |
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Springer |
Place of Publication |
Livingston, Scotland, UK |
Editor |
Margaria, T.; Melham, T.F. |
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Original Title |
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Series Title |
Lecture Notes in Computer Science |
Abbreviated Series Title |
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| Series Volume |
2144 |
Series Issue |
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Edition |
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| ISSN |
3-540-42541-1 |
ISBN |
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Approved |
yes |
| Call Number |
Sapienza @ mari @ charme01 |
Serial |
44 |
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