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Author Tronci, Enrico; Della Penna, Giuseppe; Intrigila, Benedetto; Venturini Zilli, Marisa pdf  doi
openurl 
  Title A Probabilistic Approach to Automatic Verification of Concurrent Systems Type Conference Article
  Year 2001 Publication 8th Asia-Pacific Software Engineering Conference (APSEC) Abbreviated Journal  
  Volume Issue Pages 317-324  
  Keywords  
  Abstract The main barrier to automatic verification of concurrent systems is the huge amount of memory required to complete the verification task (state explosion). In this paper we present a probabilistic algorithm for automatic verification via model checking. Our algorithm trades space with time. In particular, when memory is full because of state explosion our algorithm does not give up verification. Instead it just proceeds at a lower speed and its results will only hold with some arbitrarily small error probability. Our preliminary experimental results show that by using our probabilistic algorithm we can typically save more than 30% of RAM with an average time penalty of about 100% w.r.t. a deterministic state space exploration with enough memory to complete the verification task. This is better than giving up the verification task because of lack of memory.  
  Address  
  Corporate Author Thesis  
  Publisher IEEE Computer Society Place of Publication Macau, China Editor  
  Language Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 0-7695-1408-1 ISBN Medium  
  Area Expedition (down) Conference  
  Notes Approved yes  
  Call Number Sapienza @ mari @ apsec01 Serial 43  
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Author Tronci, Enrico; Della Penna, Giuseppe; Intrigila, Benedetto; Venturini Zilli, Marisa pdf  doi
openurl 
  Title Exploiting Transition Locality in Automatic Verification Type Conference Article
  Year 2001 Publication 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME) Abbreviated Journal  
  Volume Issue Pages 259-274  
  Keywords  
  Abstract In this paper we present an algorithm to contrast state explosion when using Explicit State Space Exploration to verify protocols. We show experimentally that protocols exhibit transition locality. We present a verification algorithm that exploits transition locality as well as an implementation of it within the Mur$\varphi$ verifier. Our algorithm is compatible with all Breadth First (BF) optimization techniques present in the Mur$\varphi$ verifier and it is by no means a substitute for any of them. In fact, since our algorithm trades space with time, it is typically most useful when one runs out of memory and has already used all other state reduction techniques present in the Mur$\varphi$ verifier. Our experimental results show that using our approach we can typically save more than 40% of RAM with an average time penalty of about 50% when using (Mur$\varphi$) bit compression and 100% when using bit compression and hash compaction.  
  Address  
  Corporate Author Thesis  
  Publisher Springer Place of Publication Livingston, Scotland, UK Editor Margaria, T.; Melham, T.F.  
  Language Summary Language Original Title  
  Series Editor Series Title Lecture Notes in Computer Science Abbreviated Series Title  
  Series Volume 2144 Series Issue Edition  
  ISSN 3-540-42541-1 ISBN Medium  
  Area Expedition (down) Conference  
  Notes Approved yes  
  Call Number Sapienza @ mari @ charme01 Serial 44  
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Author Dipoppa, G.; D'Alessandro, G.; Semprini, R.; Tronci, E. pdf  doi
openurl 
  Title Integrating Automatic Verification of Safety Requirements in Railway Interlocking System Design Type Conference Article
  Year 2001 Publication High Assurance Systems Engineering, 2001. Sixth IEEE International Symposium on Abbreviated Journal  
  Volume Issue Pages 209-219  
  Keywords  
  Abstract A railway interlocking system (RIS) is an embedded system (namely a supervisory control system) that ensures the safe, operation of the devices in a railway station. RIS is a safety critical system. We explore the possibility of integrating automatic formal verification methods in a given industry RIS design flow. The main obstructions to be overcome in our work are: selecting a formal verification tool that is efficient enough to solve the verification problems at hand; and devising a cost effective integration strategy for such tool. We were able to devise a successful integration strategy meeting the above constraints without requiring major modification in the pre-existent design flow nor retraining of personnel. We run verification experiments for a RIS designed for the Singapore Subway. The experiments show that the RIS design flow obtained from our integration strategy is able to automatically verify real life RIS designs.  
  Address  
  Corporate Author Thesis  
  Publisher IEEE Computer Society Place of Publication Albuquerque, NM, USA Editor  
  Language Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 0-7695-1275-5 ISBN Medium  
  Area Expedition (down) Conference  
  Notes Approved yes  
  Call Number Sapienza @ mari @ hase01 Serial 45  
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Author Della Penna, Giuseppe; Intrigila, Benedetto; Tronci, Enrico; Venturini Zilli, Marisa pdf  url
openurl 
  Title Synchronized Regular Expressions Type Journal Article
  Year 2002 Publication Electr. Notes Theor. Comput. Sci. Abbreviated Journal  
  Volume 62 Issue Pages 195-210  
  Keywords  
  Abstract Text manipulation is one of the most common tasks for everyone using a computer. The increasing number of textual information in electronic format that every computer user collects everyday stresses the need of more powerful tools to interact with texts. Indeed, much work has been done to provide nonprogramming tools that can be useful for the most common text manipulation issues. Regular Expressions (RE), introduced by Kleene, are well–known in the formal language theory. RE received several extensions, depending on the application of interest. In almost all the implementations of RE search algorithms (e.g. the egrep [A] UNIX command, or the Perl [17] language pattern matching constructs) we find backreferences (as defind in [1]), i.e. expressions that make reference to the string matched by a previous subexpression. Generally speaking, it seems that all the kinds of synchronizations between subexpressions in a RE can be very useful when interacting with texts. Therefore, we introduce the Synchronized Regular Expressions (SRE) as a derivation of the Regular Expressions. We use SRE to present a formal study of the already known backreferences extension, and of a new extension proposed by us, which we call the synchronized exponents. Moreover, since we are talking about formalisms that should have a practical utility and can be used in the real world, we have the problem of how to present SRE to the final users. Therefore, in this paper we also propose a user–friendly syntax for SRE to be used in implementations of SRE–powered search algorithms.  
  Address  
  Corporate Author Thesis  
  Publisher Place of Publication Editor  
  Language Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN ISBN Medium  
  Area Expedition (down) Conference  
  Notes TOSCA 2001, Theory of Concurrency, Higher Order Languages and Types Approved yes  
  Call Number Sapienza @ mari @ entcs02 Serial 46  
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Author Focardi, Riccardo; Gorrieri, Roberto; Lanotte, Ruggero; Maggiolo-Schettini, Andrea; Martinelli, Fabio; Tini, Simone; Tronci, Enrico pdf  doi
openurl 
  Title Formal Models of Timing Attacks on Web Privacy Type Journal Article
  Year 2002 Publication Electronic Notes in Theoretical Computer Science Abbreviated Journal  
  Volume 62 Issue Pages 229-243  
  Keywords  
  Abstract We model a timing attack on web privacy proposed by Felten and Schneider by using three different approaches: HL-Timed Automata, SMV model checker, and tSPA Process Algebra. Some comparative analysis on the three approaches is derived.  
  Address  
  Corporate Author Thesis  
  Publisher Place of Publication Editor  
  Language Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN ISBN Medium  
  Area Expedition (down) Conference  
  Notes TOSCA 2001, Theory of Concurrency, Higher Order Languages and Types Approved yes  
  Call Number Sapienza @ mari @ entcs02a Serial 47  
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Author Alimguzhin, V.; Mari, F.; Melatti, I.; Salvo, I.; Tronci, E. pdf  doi
openurl 
  Title Linearising Discrete Time Hybrid Systems Type Journal Article
  Year 2017 Publication IEEE Transactions on Automatic Control Abbreviated Journal  
  Volume 62 Issue 10 Pages 5357-5364  
  Keywords  
  Abstract Model Based Design approaches for embedded systems aim at generating correct-by-construction control software, guaranteeing that the closed loop system (controller and plant) meets given system level formal specifications. This technical note addresses control synthesis for safety and reachability properties of possibly non-linear discrete time hybrid systems. By means of syntactical transformations that require non-linear terms to be Lipschitz continuous functions, we over-approximate non-linear dynamics with a linear system whose controllers are guaranteed to be controllers of the original system. We evaluate performance of our approach on meaningful control synthesis benchmarks, also comparing it to a state-of-the-art tool.  
  Address  
  Corporate Author Thesis  
  Publisher Place of Publication Editor  
  Language Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 0018-9286 ISBN Medium  
  Area Expedition (down) Conference  
  Notes Approved no  
  Call Number Sapienza @ mari @ ref7902199 Serial 164  
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Author Tronci, Enrico pdf  doi
openurl 
  Title Automatic Synthesis of Control Software for an Industrial Automation Control System Type Conference Article
  Year 1999 Publication Proc.of: 14th IEEE International Conference on: Automated Software Engineering (ASE) Abbreviated Journal  
  Volume Issue Pages 247-250  
  Keywords  
  Abstract We present a case study on automatic synthesis of control software from formal specifications for an industrial automation control system. Our aim is to compare the effectiveness (i.e. design effort and controller quality) of automatic controller synthesis from closed loop formal specifications with that of manual controller design, followed by automatic verification. Our experimental results show that for industrial automation control systems, automatic synthesis is a viable and profitable (especially as far as design effort is concerned) alternative to manual design, followed by automatic verification.  
  Address  
  Corporate Author Thesis  
  Publisher Place of Publication Cocoa Beach, Florida, USA Editor  
  Language Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN ISBN Medium  
  Area Expedition (down) Conference  
  Notes Approved yes  
  Call Number Sapienza @ mari @ ase99 Serial 49  
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Author Tronci, Enrico pdf  doi
openurl 
  Title Formally Modeling a Metal Processing Plant and its Closed Loop Specifications Type Conference Article
  Year 1999 Publication 4th IEEE International Symposium on High-Assurance Systems Engineering (HASE) Abbreviated Journal  
  Volume Issue Pages 151  
  Keywords  
  Abstract We present a case study on automatic synthesis of control software from formal specifications for an industrial automation control system. Our aim is to compare the effectiveness (i.e. design effort and controller quality) of automatic controller synthesis from closed loop formal specifications with that of manual controller design followed by automatic verification. The system to be controlled (plant) models a metal processing facility near Karlsruhe. We succeeded in automatically generating C code implementing a (correct by construction) embedded controller for such a plant from closed loop formal specifications. Our experimental results show that for industrial automation control systems automatic synthesis is a viable and profitable (especially as far as design effort is concerned) alternative to manual design followed by automatic verification.  
  Address  
  Corporate Author Thesis  
  Publisher IEEE Computer Society Place of Publication Washington, D.C, USA Editor  
  Language Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 0-7695-0418-3 ISBN Medium  
  Area Expedition (down) Conference  
  Notes Approved yes  
  Call Number Sapienza @ mari @ hase99 Serial 50  
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Author Fantechi, Alessandro; Gnesi, Stefania; Mazzanti, Franco; Pugliese, Rosario; Tronci, Enrico pdf  doi
openurl 
  Title A Symbolic Model Checker for ACTL Type Conference Article
  Year 1998 Publication International Workshop on Current Trends in Applied Formal Method (FM-Trends) Abbreviated Journal  
  Volume Issue Pages 228-242  
  Keywords  
  Abstract We present SAM, a symbolic model checker for ACTL, the action-based version of CTL. SAM relies on implicit representations of Labeled Transition Systems (LTSs), the semantic domain for ACTL formulae, and uses symbolic manipulation algorithms. SAM has been realized by translating (networks of) LTSs and, possibly recursive, ACTL formulae into BSP (Boolean Symbolic Programming), a programming language aiming at defining computations on boolean functions, and by using the BSP interpreter to carry out computations (i.e. verifications).  
  Address  
  Corporate Author Thesis  
  Publisher Springer Place of Publication Boppard, Germany Editor Hutter, D.; Stephan, W.; Traverso, P.; Ullmann, M.  
  Language Summary Language Original Title  
  Series Editor Series Title Lecture Notes in Computer Science Abbreviated Series Title  
  Series Volume 1641 Series Issue Edition  
  ISSN 3-540-66462-9 ISBN Medium  
  Area Expedition (down) Conference  
  Notes Approved yes  
  Call Number Sapienza @ mari @ fm-trends98 Serial 51  
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Author Tronci, Enrico pdf  doi
openurl 
  Title Automatic Synthesis of Controllers from Formal Specifications Type Conference Article
  Year 1998 Publication Proc of 2nd IEEE International Conference on Formal Engineering Methods (ICFEM) Abbreviated Journal  
  Volume Issue Pages 134-143  
  Keywords  
  Abstract Many safety critical reactive systems are indeed embedded control systems. Usually a control system can be partitioned into two main subsystems: a controller and a plant. Roughly speaking: the controller observes the state of the plant and sends commands (stimulus) to the plant to achieve predefined goals. We show that when the plant can be modeled as a deterministic finite state system (FSS) it is possible to effectively use formal methods to automatically synthesize the program implementing the controller from the plant model and the given formal specifications for the closed loop system (plant+controller). This guarantees that the controller program is correct by construction. To the best of our knowledge there is no previously published effective algorithm to extract executable code for the controller from closed loop formal specifications. We show practical usefulness of our techniques by giving experimental results on their use to synthesize C programs implementing optimal controllers (OCs) for plants with more than 109 states.  
  Address  
  Corporate Author Thesis  
  Publisher Place of Publication Brisbane, Queensland, Australia Editor  
  Language Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN ISBN Medium  
  Area Expedition (down) Conference  
  Notes Approved yes  
  Call Number Sapienza @ mari @ icfem98 Serial 52  
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