| Records |
| Author |
Tronci, Enrico |
| Title |
Introductory Paper |
Type |
Journal Article |
| Year |
2006 |
Publication |
Sttt |
Abbreviated Journal |
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| Volume |
8 |
Issue |
4-5 |
Pages |
355-358 |
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| Abstract |
In today’s competitive market designing of digital systems (hardware as well as software) faces tremendous challenges. In fact, notwithstanding an ever decreasing project budget, time to market and product lifetime, designers are faced with an ever increasing system complexity and customer expected quality. The above situation calls for better and better formal verification techniques at all steps of the design flow. This special issue is devoted to publishing revised versions of contributions first presented at the 12th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME) held 21–24 October 2003 in L’Aquila, Italy. Authors of well regarded papers from CHARME’03 were invited to submit to this special issue. All papers included here have been suitably extended and have undergone an independent round of reviewing. |
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yes |
| Call Number |
Sapienza @ mari @ sttt06 |
Serial |
30 |
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| Author |
Della Penna, Giuseppe; Magazzeni, Daniele; Tofani, Alberto; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico |
| Title |
Automated Generation Of Optimal Controllers Through Model Checking Techniques |
Type |
Book Chapter |
| Year |
2008 |
Publication |
Informatics in Control Automation and Robotics. Selected Papers from ICINCO 2006 |
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Issue |
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Pages |
107-119 |
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Springer |
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yes |
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Sapienza @ mari @ Dmtmt08 |
Serial |
26 |
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Della Penna, Giuseppe; Tofani, Alberto; Pecorari, Marcello; Raparelli, Orazio; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico |
| Title |
A Case Study on Automated Generation of Integration Tests |
Type |
Conference Article |
| Year |
2006 |
Publication |
Fdl |
Abbreviated Journal |
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Issue |
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Pages |
278-284 |
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Ecsi |
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978-3-00-019710-9 |
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yes |
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Sapienza @ mari @ Dtprimt06 |
Serial |
27 |
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| Author |
Bartolini, Novella; Tronci, Enrico |
| Title |
On Optimizing Service Availability of an Internet Based Architecture for Infrastructure Protection |
Type |
Conference Article |
| Year |
2006 |
Publication |
Cnip |
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yes |
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Sapienza @ mari @ Bt06 |
Serial |
28 |
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| Author |
Cecconi, Michele; Tronci, Enrico |
| Title |
Requirements Formalization and Validation for a Telecommunication Equipment Protection Switcher |
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Conference Article |
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2000 |
Publication |
Hase |
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IEEE Computer Society |
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0-7695-0927-4 |
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yes |
| Call Number |
Sapienza @ mari @ CeTro00 |
Serial |
29 |
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| Author |
Cesta, Amedeo; Finzi, Alberto; Fratini, Simone; Orlandini, Andrea; Tronci, Enrico |
| Title |
Merging Planning, Scheduling & Verification – A Preliminary Analysis |
Type |
Conference Article |
| Year |
2008 |
Publication |
In Proc. of 10th ESA Workshop on Advanced Space Technologies for Robotics and Automation (ASTRA) |
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yes |
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Sapienza @ mari @ Astra08 |
Serial |
24 |
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| Author |
Cesta, Amedeo; Finzi, Alberto; Fratini, Simone; Orlandini, Andrea; Tronci, Enrico |
| Title |
Validation and Verification Issues in a Timeline-based Planning System |
Type |
Conference Article |
| Year |
2008 |
Publication |
In E-Proc. of ICAPS Workshop on Knowledge Engineering for Planning and Scheduling |
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One of the key points to take into account to foster effective introduction of AI planning and scheduling systems in real world is to develop end user trust in the related technologies. Automated planning and scheduling systems often brings solutions to the users which are neither “obvious†nor immediately acceptable for them. This is due to the ability of these tools to take into account quite an amount of temporal and causal constraints and to employ resolution processes often designed to optimize the solution with respect to non trivial evaluation functions. To increase technology trust, the study of tools for verifying and validating plans and schedules produced by AI systems might be instrumental. In general, validation and verification techniques represent a needed complementary technology in developing domain independent architectures for automated problem solving. This paper presents a preliminary report of the issues concerned with the use of two software tools for formal verification of finite state systems to the validation of the solutions produced by MrSPOCK, a recent effort for building a timeline based planning tool in an ESA project. |
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yes |
| Call Number |
Sapienza @ mari @ Keps08 |
Serial |
25 |
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| Author |
Cavaliere, Federico; Mari, Federico; Melatti, Igor; Minei, Giovanni; Salvo, Ivano; Tronci, Enrico; Verzino, Giovanni; Yushtein, Yuri |
| Title |
Model Checking Satellite Operational Procedures |
Type |
Conference Article |
| Year |
2011 |
Publication |
DAta Systems In Aerospace (DASIA), Org. EuroSpace, Canadian Space Agency, CNES, ESA, EUMETSAT. San Anton, Malta, EuroSpace. |
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We present a model checking approach for the automatic verification of satellite operational procedures (OPs). Building a model for a complex system as a satellite is a hard task. We overcome this obstruction by using a suitable simulator (SIMSAT) for the satellite. Our approach aims at improving OP quality assurance by automatic exhaustive exploration of all possible simulation scenarios. Moreover, our solution decreases OP verification costs by using a model checker (CMurphi) to automatically drive the simulator. We model OPs as user-executed programs observing the simulator telemetries and sending telecommands to the simulator. In order to assess feasibility of our approach we present experimental results on a simple meaningful scenario. Our results show that we can save up to 90% of verification time. |
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yes |
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Sapienza @ mari @ Dasia11 |
Serial |
13 |
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| Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
| Title |
From Boolean Relations to Control Software |
Type |
Conference Article |
| Year |
2011 |
Publication |
Proceedings of ICSEA 2011, The Sixth International Conference on Software Engineering Advances |
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Issue |
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Pages |
528-533 |
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Many software as well digital hardware automatic synthesis methods define the set of implementations meeting the given system specifications with a boolean relation K. In such a context a fundamental step in the software (hardware) synthesis process is finding effective solutions to the functional equation defined by K. This entails finding a (set of) boolean function(s) F (typically represented using OBDDs, Ordered Binary Decision Diagrams) such that: 1) for all x for which K is satisfiable, K(x, F(x)) = 1 holds; 2) the implementation of F is efficient with respect to given implementation parameters such as code size or execution time. While this problem has been widely studied in digital hardware synthesis, little has been done in a software synthesis context. Unfortunately the approaches developed for hardware synthesis cannot be directly used in a software context. This motivates investigation of effective methods to solve the above problem when F has to be implemented with software. In this paper we present an algorithm that, from an OBDD representation for K, generates a C code implementation for F that has the same size as the OBDD for F and a WCET (Worst Case Execution Time) linear in nr, being n = |x| the number of input arguments for functions in F and r the number of functions in F. |
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ThinkMind |
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978-1-61208-165-6 |
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Best Paper Award |
Approved |
yes |
| Call Number |
Sapienza @ mari @ icsea11 |
Serial |
14 |
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| Author |
Cesta, Amedeo; Fratini, Simone; Orlandini, Andrea; Finzi, Alberto; Tronci, Enrico |
| Title |
Flexible Plan Verification: Feasibility Results |
Type |
Journal Article |
| Year |
2011 |
Publication |
Fundamenta Informaticae |
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| Volume |
107 |
Issue |
2 |
Pages |
111-137 |
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yes |
| Call Number |
Sapienza @ mari @ fi11 |
Serial |
15 |
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