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Author |
Della Penna, Giuseppe; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico; Venturini Zilli, Marisa |
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Title |
Bounded Probabilistic Model Checking with the Mur$\varphi$ Verifier |
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Conference Article |
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Year |
2004 |
Publication |
Formal Methods in Computer-Aided Design, 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15-17, 2004, Proceedings |
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214-229 |
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In this paper we present an explicit verification algorithm for Probabilistic Systems defining discrete time/finite state Markov Chains. We restrict ourselves to verification of Bounded PCTL formulas (BPCTL), that is, PCTL formulas in which all Until operators are bounded, possibly with different bounds. This means that we consider only paths (system runs) of bounded length. Given a Markov Chain $\cal M$ and a BPCTL formula Φ, our algorithm checks if Φ is satisfied in $\cal M$. This allows to verify important properties, such as reliability in Discrete Time Hybrid Systems. We present an implementation of our algorithm within a suitable extension of the Mur$\varphi$ verifier. We call FHP-Mur$\varphi$ (Finite Horizon Probabilistic Mur$\varphi$) such extension of the Mur$\varphi$ verifier. We give experimental results comparing FHP-Mur$\varphi$ with (a finite horizon subset of) PRISM, a state-of-the-art symbolic model checker for Markov Chains. Our experimental results show that FHP-Mur$\varphi$ can effectively handle verification of BPCTL formulas for systems that are out of reach for PRISM, namely those involving arithmetic operations on the state variables (e.g. hybrid systems). |
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Springer |
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Hu, A.J.; Martin, A.K. |
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Lecture Notes in Computer Science |
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Series Volume |
3312 |
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3-540-23738-0 |
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yes |
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Call Number |
Sapienza @ mari @ Dimtz04 |
Serial |
87 |
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Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Title |
Synthesizing Control Software from Boolean Relations |
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Journal Article |
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Year |
2012 |
Publication |
International Journal on Advances in Software |
Abbreviated Journal |
Intern. Journal on Advances in SW |
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vol. 5, nr 3&4 |
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Pages |
212-223 |
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Keywords |
Control Software Synthesis; Embedded Systems; Model Checking |
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Abstract |
Many software as well digital hardware automatic
synthesis methods define the set of
implementations meeting the given system
specifications with a boolean relation K. In
such a context a fundamental step in the software
(hardware) synthesis process is finding effective
solutions to the functional equation defined by
K. This entails finding a (set of) boolean
function(s) F (typically represented using
OBDDs, Ordered Binary Decision Diagrams)
such that: 1) for all x for which K is
satisfiable, K(x, F(x)) = 1 holds; 2) the
implementation of F is efficient with respect
to given implementation parameters such as code
size or execution time. While this problem has
been widely studied in digital hardware synthesis,
little has been done in a software synthesis
context. Unfortunately, the approaches developed
for hardware synthesis cannot be directly used in
a software context. This motivates investigation
of effective methods to solve the above problem
when F has to be implemented with software. In
this paper, we present an algorithm that, from an
OBDD representation for K, generates a C code
implementation for F that has the same size as
the OBDD for F and a worst case execution time
linear in nr, being n = |x| the number of
input arguments for functions in F and r the
number of functions in F. Moreover, a formal
proof of the proposed algorithm correctness is
also shown. Finally, we present experimental
results showing effectiveness of the proposed
algorithm. |
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IARIA |
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Editor |
Luigi Lavazza |
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ISSN |
1942-2628 |
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yes |
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Call Number |
Sapienza @ melatti @ |
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108 |
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Author |
Dipoppa, G.; D'Alessandro, G.; Semprini, R.; Tronci, E. |
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Title |
Integrating Automatic Verification of Safety Requirements in Railway Interlocking System Design |
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Conference Article |
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Year |
2001 |
Publication |
High Assurance Systems Engineering, 2001. Sixth IEEE International Symposium on |
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209-219 |
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A railway interlocking system (RIS) is an embedded system (namely a supervisory control system) that ensures the safe, operation of the devices in a railway station. RIS is a safety critical system. We explore the possibility of integrating automatic formal verification methods in a given industry RIS design flow. The main obstructions to be overcome in our work are: selecting a formal verification tool that is efficient enough to solve the verification problems at hand; and devising a cost effective integration strategy for such tool. We were able to devise a successful integration strategy meeting the above constraints without requiring major modification in the pre-existent design flow nor retraining of personnel. We run verification experiments for a RIS designed for the Singapore Subway. The experiments show that the RIS design flow obtained from our integration strategy is able to automatically verify real life RIS designs. |
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IEEE Computer Society |
Place of Publication |
Albuquerque, NM, USA |
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0-7695-1275-5 |
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yes |
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Call Number |
Sapienza @ mari @ hase01 |
Serial |
45 |
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Author |
Della Penna, Giuseppe; Intrigila, Benedetto; Tronci, Enrico; Venturini Zilli, Marisa |
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Title |
Exploiting Transition Locality in the Disk Based Mur$\varphi$ Verifier |
Type |
Conference Article |
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Year |
2002 |
Publication |
4th International Conference on Formal Methods in Computer-Aided Design (FMCAD) |
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Pages |
202-219 |
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The main obstruction to automatic verification of Finite State Systems is the huge amount of memory required to complete the verification task (state explosion). This motivates research on distributed as well as disk based verification algorithms. In this paper we present a disk based Breadth First Explicit State Space Exploration algorithm as well as an implementation of it within the Mur$\varphi$ verifier. Our algorithm exploits transition locality (i.e. the statistical fact that most transitions lead to unvisited states or to recently visited states) to decrease disk read accesses thus reducing the time overhead due to disk usage. A disk based verification algorithm for Mur$\varphi$ has been already proposed in the literature. To measure the time speed up due to locality exploitation we compared our algorithm with such previously proposed algorithm. Our experimental results show that our disk based verification algorithm is typically more than 10 times faster than such previously proposed disk based verification algorithm. To measure the time overhead due to disk usage we compared our algorithm with RAM based verification using the (standard) Mur$\varphi$ verifier with enough memory to complete the verification task. Our experimental results show that even when using 1/10 of the RAM needed to complete verification, our disk based algorithm is only between 1.4 and 5.3 times (3 times on average) slower than (RAM) Mur$\varphi$ with enough RAM memory to complete the verification task at hand. Using our disk based Mur$\varphi$ we were able to complete verification of a protocol with about $10^9$ reachable states. This would require more than 5 gigabytes of RAM using RAM based Mur$\varphi$. |
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Springer |
Place of Publication |
Portland, OR, USA |
Editor |
Aagaard, M.; O'Leary, J.W. |
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Lecture Notes in Computer Science |
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Series Volume |
2517 |
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ISSN |
3-540-00116-6 |
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yes |
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Call Number |
Sapienza @ mari @ fmcad02 |
Serial |
41 |
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Author |
Della Penna, Giuseppe; Intrigila, Benedetto; Tronci, Enrico; Venturini Zilli, Marisa |
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Title |
Synchronized Regular Expressions |
Type |
Journal Article |
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Year |
2002 |
Publication |
Electr. Notes Theor. Comput. Sci. |
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62 |
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195-210 |
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Abstract |
Text manipulation is one of the most common tasks for everyone using a computer. The increasing number of textual information in electronic format that every computer user collects everyday stresses the need of more powerful tools to interact with texts. Indeed, much work has been done to provide nonprogramming tools that can be useful for the most common text manipulation issues. Regular Expressions (RE), introduced by Kleene, are well–known in the formal language theory. RE received several extensions, depending on the application of interest. In almost all the implementations of RE search algorithms (e.g. the egrep [A] UNIX command, or the Perl [17] language pattern matching constructs) we find backreferences (as defind in [1]), i.e. expressions that make reference to the string matched by a previous subexpression. Generally speaking, it seems that all the kinds of synchronizations between subexpressions in a RE can be very useful when interacting with texts. Therefore, we introduce the Synchronized Regular Expressions (SRE) as a derivation of the Regular Expressions. We use SRE to present a formal study of the already known backreferences extension, and of a new extension proposed by us, which we call the synchronized exponents. Moreover, since we are talking about formalisms that should have a practical utility and can be used in the real world, we have the problem of how to present SRE to the final users. Therefore, in this paper we also propose a user–friendly syntax for SRE to be used in implementations of SRE–powered search algorithms. |
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Notes |
TOSCA 2001, Theory of Concurrency, Higher Order Languages and Types |
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yes |
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Call Number |
Sapienza @ mari @ entcs02 |
Serial |
46 |
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Author |
Tronci, Enrico |
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Title |
Equational Programming in lambda-calculus |
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Conference Article |
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Year |
1991 |
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Sixth Annual IEEE Symposium on Logic in Computer Science (LICS) |
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191-202 |
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IEEE Computer Society |
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Amsterdam, The Netherlands |
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yes |
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Call Number |
Sapienza @ mari @ lics91 |
Serial |
58 |
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Author |
Tronci, Enrico |
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Title |
Equational Programming in Lambda-Calculus via SL-Systems. Part 2 |
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1996 |
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Theoretical Computer Science |
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160 |
Issue |
1&2 |
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185-216 |
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yes |
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Sapienza @ mari @ tcs96a |
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55 |
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Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Title |
Synthesis of Quantized Feedback Control Software for Discrete Time Linear Hybrid Systems |
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Conference Article |
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2010 |
Publication |
Computer Aided Verification |
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180-195 |
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We present an algorithm that given a Discrete Time Linear Hybrid System returns a correct-by-construction software implementation K for a (near time optimal) robust quantized feedback controller for along with the set of states on which K is guaranteed to work correctly (controllable region). Furthermore, K has a Worst Case Execution Time linear in the number of bits of the quantization schema. |
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Springer Berlin / Heidelberg |
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Touili, T.; Cook, B.; Jackson, P. |
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Lecture Notes in Computer Science |
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Series Volume |
6174 |
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yes |
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Sapienza @ mari @ cav2010 |
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16 |
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Author |
Gorrieri, Roberto; Lanotte, Ruggero; Maggiolo-Schettini, Andrea; Martinelli, Fabio; Tini, Simone; Tronci, Enrico |
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Title |
Automated analysis of timed security: a case study on web privacy |
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2004 |
Publication |
International Journal of Information Security |
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2 |
Issue |
3-4 |
Pages |
168-186 |
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This paper presents a case study on an automated analysis of real-time security models. The case study on a web system (originally proposed by Felten and Schneider) is presented that shows a timing attack on the privacy of browser users. Three different approaches are followed: LH-Timed Automata (analyzed using the model checker HyTech), finite-state automata (analyzed using the model checker NuSMV), and process algebras (analyzed using the model checker CWB-NC). A comparative analysis of these three approaches is given. |
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yes |
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Call Number |
Sapienza @ mari @ ijis04 |
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33 |
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Author |
Della Penna, Giuseppe; Di Marco, Antinisca; Intrigila, Benedetto; Melatti, Igor; Pierantonio, Alfonso |
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Title |
Interoperability mapping from XML schemas to ER diagrams |
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Journal Article |
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Year |
2006 |
Publication |
Data Knowl. Eng. |
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Volume |
59 |
Issue |
1 |
Pages |
166-188 |
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The eXtensible Markup Language (XML) is a de facto standard on the Internet and is now being used to exchange a variety of data structures. This leads to the problem of efficiently storing, querying and retrieving a great amount of data contained in XML documents. Unfortunately, XML data often need to coexist with historical data. At present, the best solution for storing XML into pre-existing data structures is to extract the information from the XML documents and adapt it to the data structures’ logical model (e.g., the relational model of a DBMS). In this paper, we introduce a technique called Xere (XML entity–relationship exchange) to assist the integration of XML data with other data sources. To this aim, we present an algorithm that maps XML schemas into entity–relationship diagrams, discuss its soundness and completeness and show its implementation in XSLT. |
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Elsevier Science Publishers B. V. |
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Amsterdam, The Netherlands, The Netherlands |
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0169-023x |
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yes |
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Call Number |
Sapienza @ mari @ Ddimp06 |
Serial |
77 |
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