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Author  |
Mancini, T.; Melatti, I.; Tronci, E. |
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Title |
Any-horizon uniform random sampling and enumeration of constrained scenarios for simulation-based formal verification |
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Year |
2021 |
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IEEE Transactions on Software Engineering |
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1-1 |
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Model-based approaches to the verification of non-terminating Cyber-Physical Systems (CPSs) usually rely on numerical simulation of the System Under Verification (SUV) model under input scenarios of possibly varying duration, chosen among those satisfying given constraints. Such constraints typically stem from requirements (or assumptions) on the SUV inputs and its operational environment as well as from the enforcement of additional conditions aiming at, e.g., prioritising the (often extremely long) verification activity, by, e.g., focusing on scenarios explicitly exercising selected requirements, or avoiding </i>vacuity</i> in their satisfaction. In this setting, the possibility to efficiently sample at random (with a known distribution, e.g., uniformly) within, or to efficiently enumerate (possibly in a uniformly random order) scenarios among those satisfying all the given constraints is a key enabler for the practical viability of the verification process, e.g., via simulation-based statistical model checking. Unfortunately, in case of non-trivial combinations of constraints, iterative approaches like Markovian random walks in the space of sequences of inputs in general fail in extracting scenarios according to a given distribution (e.g., uniformly), and can be very inefficient to produce at all scenarios that are both legal (with respect to SUV assumptions) and of interest (with respect to the additional constraints). For example, in our case studies, up to 91% of the scenarios generated using such iterative approaches would need to be neglected. In this article, we show how, given a set of constraints on the input scenarios succinctly defined by multiple finite memory monitors, a data structure (scenario generator) can be synthesised, from which any-horizon scenarios satisfying the input constraints can be efficiently extracted by (possibly uniform) random sampling or (randomised) enumeration. Our approach enables seamless support to virtually all simulation-based approaches to CPS verification, ranging from simple random testing to statistical model checking and formal (i.e., exhaustive) verification, when a suitable bound on the horizon or an iterative horizon enlargement strategy is defined, as in the spirit of bounded model checking. |
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1939-3520 |
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MCLab @ davi @ ref9527998 |
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191 |
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Author |
Mancini, T.; Tronci, E.; Scialanca, A.; Lanciotti, F.; Finzi, A.; Guarneri, R.; Di Pompeo, S. |
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Title |
Optimal Fault-Tolerant Placement of Relay Nodes in a Mission Critical Wireless Network |
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Conference Article |
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2018 |
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25th RCRA International Workshop on “Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion” (RCRA 2018) |
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MCLab @ davi @ |
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174 |
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Author |
Mancini, Toni ; Mari, Federico ; Massini, Annalisa; Melatti, Igor; Tronci, Enrico |
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Title |
System Level Formal Verification via Distributed Multi-Core Hardware in the Loop Simulation |
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Conference Article |
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2014 |
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Proc. of the 22nd Euromicro International Conference on Parallel, Distributed and Network-Based Processing |
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Euromicro International Conference on Parallel, Distributed and Network-Based Processing |
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IEEE Computer Society |
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Call Number |
Sapienza @ melatti @ |
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118 |
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Mancini, Toni; Mari, Federico; Massini, Annalisa; Melatti, Igor; Merli, Fabio; Tronci, Enrico |
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Title |
System Level Formal Verification via Model Checking Driven Simulation |
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Conference Article |
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2013 |
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Proceedings of the 25th International Conference on Computer Aided Verification. July 13-19, 2013, Saint Petersburg, Russia |
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CAV 2013 |
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296-312 |
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Springer - Verlag |
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Lecture Notes in Computer Science |
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8044 |
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0302-9743 |
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978-3-642-39798-1 |
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yes |
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Call Number |
Sapienza @ mari @ |
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113 |
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Author |
Mancini, Toni; Mari, Federico; Massini, Annalisa; Melatti, Igor; Tronci, Enrico |
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Title |
Anytime System Level Verification via Random Exhaustive Hardware In The Loop Simulation |
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Conference Article |
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2014 |
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In Proceedings of 17th EuroMicro Conference on Digital System Design (DSD 2014) |
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Call Number |
MCLab @ davi @ |
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122 |
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Author |
Mancini, Toni; Mari, Federico; Massini, Annalisa; Melatti, Igor; Tronci, Enrico |
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Title |
SyLVaaS: System Level Formal Verification as a Service |
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Conference Article |
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2015 |
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Proceedings of the 23rd Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP 2015), special session on Formal Approaches to Parallel and Distributed Systems (4PAD) |
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MCLab @ davi @ |
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123 |
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Author |
Mancini, Toni; Mari, Federico; Massini, Annalisa; Melatti, Igor; Tronci, Enrico |
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Title |
Simulator Semantics for System Level Formal Verification |
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Conference Article |
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2015 |
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Proceedings Sixth International Symposium on Games, Automata, Logics and Formal Verification (GandALF 2015), |
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Call Number |
MCLab @ davi @ |
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125 |
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Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Title |
Synthesizing Control Software from Boolean Relations |
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Journal Article |
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Year |
2012 |
Publication |
International Journal on Advances in Software |
Abbreviated Journal |
Intern. Journal on Advances in SW |
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Volume |
vol. 5, nr 3&4 |
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Pages |
212-223 |
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Keywords |
Control Software Synthesis; Embedded Systems; Model Checking |
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Abstract |
Many software as well digital hardware automatic
synthesis methods define the set of
implementations meeting the given system
specifications with a boolean relation K. In
such a context a fundamental step in the software
(hardware) synthesis process is finding effective
solutions to the functional equation defined by
K. This entails finding a (set of) boolean
function(s) F (typically represented using
OBDDs, Ordered Binary Decision Diagrams)
such that: 1) for all x for which K is
satisfiable, K(x, F(x)) = 1 holds; 2) the
implementation of F is efficient with respect
to given implementation parameters such as code
size or execution time. While this problem has
been widely studied in digital hardware synthesis,
little has been done in a software synthesis
context. Unfortunately, the approaches developed
for hardware synthesis cannot be directly used in
a software context. This motivates investigation
of effective methods to solve the above problem
when F has to be implemented with software. In
this paper, we present an algorithm that, from an
OBDD representation for K, generates a C code
implementation for F that has the same size as
the OBDD for F and a worst case execution time
linear in nr, being n = |x| the number of
input arguments for functions in F and r the
number of functions in F. Moreover, a formal
proof of the proposed algorithm correctness is
also shown. Finally, we present experimental
results showing effectiveness of the proposed
algorithm. |
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IARIA |
Place of Publication |
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Editor |
Luigi Lavazza |
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ISSN |
1942-2628 |
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Approved |
yes |
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Call Number |
Sapienza @ melatti @ |
Serial |
108 |
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Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Title |
Linear Constraints and Guarded Predicates as a Modeling Language for Discrete Time Hybrid Systems |
Type |
Journal Article |
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Year |
2013 |
Publication |
International Journal on Advances in Software |
Abbreviated Journal |
Intern. Journal on Advances in SW |
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Volume |
vol. 6, nr 1&2 |
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Pages |
155-169 |
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Keywords |
Model-based software design; Linear predicates; Hybrid systems |
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Abstract |
Model based design is particularly appealing in
software based control systems (e.g., embedded
software) design, since in such a case system
level specifications are much easier to define
than the control software behavior itself. In
turn, model based design of embedded systems
requires modeling both continuous subsystems
(typically, the plant) as well as discrete
subsystems (the controller). This is typically
done using hybrid systems. Mixed Integer Linear
Programming (MILP) based abstraction techniques
have been successfully applied to automatically
synthesize correct-by-construction control
software for discrete time linear hybrid systems,
where plant dynamics is modeled as a linear
predicate over state, input, and next state
variables. Unfortunately, MILP solvers require
such linear predicates to be conjunctions of
linear constraints, which is not a natural way of
modeling hybrid systems. In this paper we show
that, under the hypothesis that each variable
ranges over a bounded interval, any linear
predicate built upon conjunction and disjunction
of linear constraints can be automatically
translated into an equivalent conjunctive
predicate. Since variable bounds play a key role
in this translation, our algorithm includes a
procedure to compute all implicit variable bounds
of the given linear predicate. Furthermore, we
show that a particular form of linear predicates,
namely guarded predicates, are a natural and
powerful language to succinctly model discrete
time linear hybrid systems dynamics. Finally, we
experimentally show the feasibility of our
approach on an important and challenging case
study taken from the literature, namely the
multi-input Buck DC-DC Converter. As an example,
the guarded predicate that models (with 57
constraints) a 6-inputs Buck DC-DC Converter is
translated in a conjunctive predicate (with 102
linear constraints) in about 40 minutes. |
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IARIA |
Place of Publication |
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Editor |
Luigi Lavazza |
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ISSN |
1942-2628 |
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Approved |
yes |
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Call Number |
Sapienza @ melatti @ |
Serial |
115 |
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Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Title |
From Boolean Relations to Control Software |
Type |
Conference Article |
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Year |
2011 |
Publication |
Proceedings of ICSEA 2011, The Sixth International Conference on Software Engineering Advances |
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Issue |
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Pages |
528-533 |
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Abstract |
Many software as well digital hardware automatic synthesis methods define the set of implementations meeting the given system specifications with a boolean relation K. In such a context a fundamental step in the software (hardware) synthesis process is finding effective solutions to the functional equation defined by K. This entails finding a (set of) boolean function(s) F (typically represented using OBDDs, Ordered Binary Decision Diagrams) such that: 1) for all x for which K is satisfiable, K(x, F(x)) = 1 holds; 2) the implementation of F is efficient with respect to given implementation parameters such as code size or execution time. While this problem has been widely studied in digital hardware synthesis, little has been done in a software synthesis context. Unfortunately the approaches developed for hardware synthesis cannot be directly used in a software context. This motivates investigation of effective methods to solve the above problem when F has to be implemented with software. In this paper we present an algorithm that, from an OBDD representation for K, generates a C code implementation for F that has the same size as the OBDD for F and a WCET (Worst Case Execution Time) linear in nr, being n = |x| the number of input arguments for functions in F and r the number of functions in F. |
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ThinkMind |
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978-1-61208-165-6 |
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Best Paper Award |
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yes |
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Call Number |
Sapienza @ mari @ icsea11 |
Serial |
14 |
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