| Records |
| Author |
Bobbio, Andrea; Bologna, Sandro; Minichino, Michele; Ciancamerla, Ester; Incalcaterra, Piero; Kropp, Corrado; Tronci, Enrico |
| Title |
Advanced techniques for safety analysis applied to the gas turbine control system of Icaro co generative plant |
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Conference Article |
| Year |
2001 |
Publication |
X Convegno Tecnologie e Sistemi Energetici Complessi |
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339-350 |
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The paper describes two complementary and integrable approaches, a probabilistic one and a deterministic one, based on classic and advanced modelling techniques for safety analysis of complex computer based systems. The probabilistic approach is based on classical and innovative probabilistic analysis methods. The deterministic approach is based on formal verification methods. Such approaches are applied to the gas turbine control system of ICARO co generative plant, in operation at ENEA CR Casaccia. The main difference between the two approaches, behind the underlining different theories, is that the probabilistic one addresses the control system by itself, as the set of sensors, processing units and actuators, while the deterministic one also includes the behaviour of the equipment under control which interacts with the control system. The final aim of the research, documented in this paper, is to explore an innovative method which put the probabilistic and deterministic approaches in a strong relation to overcome the drawbacks of their isolated, selective and fragmented use which can lead to inconsistencies in the evaluation results. |
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Genova, Italy |
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yes |
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Sapienza @ mari @ tesec01 |
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65 |
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| Author |
Coppo, Mario; Dezani-Ciancaglini, Mariangiola; Giovannetti, Elio; Salvo, Ivano |
| Title |
Mobility Types for Mobile Processes in Mobile Ambients |
Type |
Journal Article |
| Year |
2003 |
Publication |
Electr. Notes Theor. Comput. Sci. |
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78 |
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We present an ambient-like calculus in which the open capability is dropped, and a new form of “lightweight  process mobility is introduced. The calculus comes equipped with a type system that allows the kind of values exchanged in communications and the access and mobility properties of processes to be controlled. A type inference procedure determines the “minimal  requirements to accept a system or a component as well typed. This gives a kind of principal typing. As an expressiveness test, we show that some well known calculi of concurrency and mobility can be encoded in our calculus in a natural way. |
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yes |
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Sapienza @ mari @ Coppo-Dezani-Giovannetti-Salvo:03 |
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74 |
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Della Penna, Giuseppe; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico; Venturini Zilli, Marisa |
| Title |
Exploiting Transition Locality in Automatic Verification of Finite State Concurrent Systems |
Type |
Journal Article |
| Year |
2004 |
Publication |
Sttt |
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6 |
Issue |
4 |
Pages |
320-341 |
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In this paper we show that statistical properties of the transition graph of a system to be verified can be exploited to improve memory or time performances of verification algorithms. We show experimentally that protocols exhibit transition locality. That is, with respect to levels of a breadth-first state space exploration, state transitions tend to be between states belonging to close levels of the transition graph. We support our claim by measuring transition locality for the set of protocols included in the Mur$\varphi$ verifier distribution. We present a cache-based verification algorithm that exploits transition locality to decrease memory usage and a disk-based verification algorithm that exploits transition locality to decrease disk read accesses, thus reducing the time overhead due to disk usage. Both algorithms have been implemented within the Mur$\varphi$ verifier. Our experimental results show that our cache-based algorithm can typically save more than 40% of memory with an average time penalty of about 50% when using (Mur$\varphi$) bit compression and 100% when using bit compression and hash compaction, whereas our disk-based verification algorithm is typically more than ten times faster than a previously proposed disk-based verification algorithm and, even when using 10% of the memory needed to complete verification, it is only between 40 and 530% (300% on average) slower than (RAM) Mur$\varphi$ with enough memory to complete the verification task at hand. Using just 300 MB of memory our disk-based Mur$\varphi$ was able to complete verification of a protocol with about $10^9$ reachable states. This would require more than 5 GB of memory using standard Mur$\varphi$. |
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yes |
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Sapienza @ mari @ DIMTZ04j |
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91 |
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