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Author Tronci, Enrico; Della Penna, Giuseppe; Intrigila, Benedetto; Venturini Zilli, Marisa
Title A Probabilistic Approach to Automatic Verification of Concurrent Systems Type Conference Article
Year 2001 Publication 8th Asia-Pacific Software Engineering Conference (APSEC) Abbreviated Journal
Volume Issue Pages 317-324
Keywords
Abstract The main barrier to automatic verification of concurrent systems is the huge amount of memory required to complete the verification task (state explosion). In this paper we present a probabilistic algorithm for automatic verification via model checking. Our algorithm trades space with time. In particular, when memory is full because of state explosion our algorithm does not give up verification. Instead it just proceeds at a lower speed and its results will only hold with some arbitrarily small error probability. Our preliminary experimental results show that by using our probabilistic algorithm we can typically save more than 30% of RAM with an average time penalty of about 100% w.r.t. a deterministic state space exploration with enough memory to complete the verification task. This is better than giving up the verification task because of lack of memory.
Address
Corporate Author Thesis
Publisher (down) IEEE Computer Society Place of Publication Macau, China Editor
Language Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN 0-7695-1408-1 ISBN Medium
Area Expedition Conference
Notes Approved yes
Call Number Sapienza @ mari @ apsec01 Serial 43
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Author Dipoppa, G.; D'Alessandro, G.; Semprini, R.; Tronci, E.
Title Integrating Automatic Verification of Safety Requirements in Railway Interlocking System Design Type Conference Article
Year 2001 Publication High Assurance Systems Engineering, 2001. Sixth IEEE International Symposium on Abbreviated Journal
Volume Issue Pages 209-219
Keywords
Abstract A railway interlocking system (RIS) is an embedded system (namely a supervisory control system) that ensures the safe, operation of the devices in a railway station. RIS is a safety critical system. We explore the possibility of integrating automatic formal verification methods in a given industry RIS design flow. The main obstructions to be overcome in our work are: selecting a formal verification tool that is efficient enough to solve the verification problems at hand; and devising a cost effective integration strategy for such tool. We were able to devise a successful integration strategy meeting the above constraints without requiring major modification in the pre-existent design flow nor retraining of personnel. We run verification experiments for a RIS designed for the Singapore Subway. The experiments show that the RIS design flow obtained from our integration strategy is able to automatically verify real life RIS designs.
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Corporate Author Thesis
Publisher (down) IEEE Computer Society Place of Publication Albuquerque, NM, USA Editor
Language Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN 0-7695-1275-5 ISBN Medium
Area Expedition Conference
Notes Approved yes
Call Number Sapienza @ mari @ hase01 Serial 45
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Author Tronci, Enrico
Title Formally Modeling a Metal Processing Plant and its Closed Loop Specifications Type Conference Article
Year 1999 Publication 4th IEEE International Symposium on High-Assurance Systems Engineering (HASE) Abbreviated Journal
Volume Issue Pages 151
Keywords
Abstract We present a case study on automatic synthesis of control software from formal specifications for an industrial automation control system. Our aim is to compare the effectiveness (i.e. design effort and controller quality) of automatic controller synthesis from closed loop formal specifications with that of manual controller design followed by automatic verification. The system to be controlled (plant) models a metal processing facility near Karlsruhe. We succeeded in automatically generating C code implementing a (correct by construction) embedded controller for such a plant from closed loop formal specifications. Our experimental results show that for industrial automation control systems automatic synthesis is a viable and profitable (especially as far as design effort is concerned) alternative to manual design followed by automatic verification.
Address
Corporate Author Thesis
Publisher (down) IEEE Computer Society Place of Publication Washington, D.C, USA Editor
Language Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN 0-7695-0418-3 ISBN Medium
Area Expedition Conference
Notes Approved yes
Call Number Sapienza @ mari @ hase99 Serial 50
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Author Tronci, Enrico
Title Hardware Verification, Boolean Logic Programming, Boolean Functional Programming Type Conference Article
Year 1995 Publication Tenth Annual IEEE Symposium on Logic in Computer Science (LICS) Abbreviated Journal
Volume Issue Pages 408-418
Keywords
Abstract One of the main obstacles to automatic verification of finite state systems (FSSs) is state explosion. In this respect automatic verification of an FSS M using model checking and binary decision diagrams (BDDs) has an intrinsic limitation: no automatic global optimization of the verification task is possible until a BDD representation for M is generated. This is because systems and specifications are defined using different languages. To perform global optimization before generating a BDD representation for M we propose to use the same language to define systems and specifications. We show that first order logic on a Boolean domain yields an efficient functional programming language that can be used to represent, specify and automatically verify FSSs, e.g. on a SUN Sparc Station 2 we were able to automatically verify a 64 bit commercial multiplier.
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Corporate Author Thesis
Publisher (down) IEEE Computer Society Place of Publication San Diego, California Editor
Language Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN ISBN Medium
Area Expedition Conference
Notes Approved yes
Call Number Sapienza @ mari @ lics95 Serial 56
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Author Tronci, Enrico
Title Equational Programming in lambda-calculus Type Conference Article
Year 1991 Publication Sixth Annual IEEE Symposium on Logic in Computer Science (LICS) Abbreviated Journal
Volume Issue Pages 191-202
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Abstract
Address
Corporate Author Thesis
Publisher (down) IEEE Computer Society Place of Publication Amsterdam, The Netherlands Editor
Language Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN ISBN Medium
Area Expedition Conference
Notes Approved yes
Call Number Sapienza @ mari @ lics91 Serial 58
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Author Böhm, Corrado; Tronci, Enrico
Title X-Separability and Left-Invertibility in lambda-calculus Type Conference Article
Year 1987 Publication Symposium on Logic in Computer Science (LICS) Abbreviated Journal
Volume Issue Pages 320-328
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Abstract
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Corporate Author Thesis
Publisher (down) IEEE Computer Society Place of Publication Ithaca, New York, USA Editor
Language Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN ISBN Medium
Area Expedition Conference
Notes Approved yes
Call Number Sapienza @ mari @ lics87 Serial 63
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Author Tronci, Enrico
Title On Computing Optimal Controllers for Finite State Systems Type Conference Article
Year 1997 Publication CDC '97: Proceedings of the 36th IEEE International Conference on Decision and Control Abbreviated Journal
Volume Issue Pages
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Abstract
Address
Corporate Author Thesis
Publisher (down) IEEE Computer Society Place of Publication Washington, DC, USA Editor
Language Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN ISBN Medium
Area Expedition Conference
Notes Approved yes
Call Number Sapienza @ mari @ cdc97 Serial 66
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Author Tronci, Enrico
Title Optimal Finite State Supervisory Control Type Conference Article
Year 1996 Publication CDC '96: Proceedings of the 35th IEEE International Conference on Decision and Control Abbreviated Journal
Volume Issue Pages
Keywords
Abstract Supervisory Controllers are Discrete Event Dynamic Systems (DEDSs) forming the discrete core of a Hybrid Control System. We address the problem of automatic synthesis of Optimal Finite State Supervisory Controllers (OSCs). We show that Boolean First Order Logic (BFOL) and Binary Decision Diagrams (BDDs) are an effective methodological and practical framework for Optimal Finite State Supervisory Control. Using BFOL programs (i.e. systems of boolean functional equations) and BDDs we give a symbolic (i.e. BDD based) algorithm for automatic synthesis of OSCs. Our OSC synthesis algorithm can handle arbitrary sets of final states as well as plant transition relations containing loops and uncontrollable events (e.g. failures). We report on experimental results on the use of our OSC synthesis algorithm to synthesize a C program implementing a minimum fuel OSC for two autonomous vehicles moving on a 4 x 4 grid.
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Corporate Author Thesis
Publisher (down) IEEE Computer Society Place of Publication Washington, DC, USA Editor
Language Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN ISBN Medium
Area Expedition Conference
Notes Approved yes
Call Number Sapienza @ mari @ cdc96 Serial 67
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Author Bucciarelli, Antonio; de Lorenzis, Silvia; Piperno, Adolfo; Salvo, Ivano
Title Some Computational Properties of Intersection Types (Extended Abstract) Type Journal Article
Year 1999 Publication Abbreviated Journal
Volume Issue Pages 109-118
Keywords lambda calculusCurry types, intersection types, lambda-definability, lambda-terms, strong normalization
Abstract This paper presents a new method for comparing computation-properties of λ-terms typeable with intersection types with respect to terms typeable with Curry types. In particular, strong normalization and λ-definability are investigated. A translation is introduced from intersection typing derivations to Curry typeable terms; the main feature of the proposed technique is that the translation is preserved by β-reduction. This allows to simulate a computation starting from a term typeable in the intersection discipline by means of a computation starting from a simply typeable term. Our approach naturally leads to prove strong normalization in the intersection system by means of purely syntactical techniques. In addition, the presented method enables us to give a proof of a conjecture proposed by Leivant in 1990, namely that all functions uniformly definable using intersection types are already definable using Curry types.
Address
Corporate Author Thesis
Publisher (down) IEEE Computer Society Place of Publication Editor
Language Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN ISBN Medium
Area Expedition Conference
Notes Approved yes
Call Number Sapienza @ mari @ bucciarelli-delorenzis-piperno-salvo:99 Serial 71
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Author Intrigila, Benedetto; Magazzeni, Daniele; Melatti, Igor; Tronci, Enrico
Title A Model Checking Technique for the Verification of Fuzzy Control Systems Type Conference Article
Year 2005 Publication CIMCA '05: Proceedings of the International Conference on Computational Intelligence for Modelling, Control and Automation and International Conference on Intelligent Agents, Web Technologies and Internet Commerce Vol-1 (CIMCA-IAWTIC'06) Abbreviated Journal
Volume Issue Pages 536-542
Keywords
Abstract Fuzzy control is well known as a powerful technique for designing and realizing control systems. However, statistical evidence for their correct behavior may be not enough, even when it is based on a large number of samplings. In order to provide a more systematic verification process, the cell-to-cell mapping technology has been used in a number of cases as a verification tool for fuzzy control systems and, more recently, to assess their optimality and robustness. However, cell-to-cell mapping is typically limited in the number of cells it can explore. To overcome this limitation, in this paper we show how model checking techniques may be instead used to verify the correct behavior of a fuzzy control system. To this end, we use a modified version of theMurphi verifier, which ease the modeling phase by allowing to use finite precision real numbers and external C functions. In this way, also already designed simulators may be used for the verification phase. With respect to the cell mapping technique, our approach appears to be complementary; indeed, it explores a much larger number of states, at the cost of being less informative on the global dynamic of the system.
Address
Corporate Author Thesis
Publisher (down) IEEE Computer Society Place of Publication Washington, DC, USA Editor
Language Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN 0-7695-2504-0-01 ISBN Medium
Area Expedition Conference
Notes Approved yes
Call Number Sapienza @ mari @ Immt05 Serial 75
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