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Author |
Cesta, Amedeo; Finzi, Alberto; Fratini, Simone; Orlandini, Andrea; Tronci, Enrico |
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Title |
Verifying Flexible Timeline-based Plans |
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Conference Article |
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2009 |
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E-Proc. of ICAPS Workshop on Validation and Verification of Planning and Scheduling Systems |
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The synthesis of flexible temporal plans has demonstrated wide applications possibilities in heterogeneous domains. We are currently studying the connection between plan generation and execution from the particular perspective of verifying a flexible plan before actual execution. This paper explores how a model-checking verification tool, based on UPPAAL-TIGA, is suitable for verifying flexible temporal plans. We first describe the formal model, the formalism, and the verification method. Furthermore we discuss our own approach and some preliminary empirical results using a real-world case study. |
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yes |
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Sapienza @ mari @ Vvps09 |
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23 |
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Author |
Cesta, Amedeo; Finzi, Alberto; Fratini, Simone; Orlandini, Andrea; Tronci, Enrico |
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Title |
Merging Planning, Scheduling & Verification – A Preliminary Analysis |
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2008 |
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In Proc. of 10th ESA Workshop on Advanced Space Technologies for Robotics and Automation (ASTRA) |
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yes |
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Sapienza @ mari @ Astra08 |
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24 |
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Cesta, Amedeo; Finzi, Alberto; Fratini, Simone; Orlandini, Andrea; Tronci, Enrico |
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Title |
Validation and Verification Issues in a Timeline-based Planning System |
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Conference Article |
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2008 |
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In E-Proc. of ICAPS Workshop on Knowledge Engineering for Planning and Scheduling |
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One of the key points to take into account to foster effective introduction of AI planning and scheduling systems in real world is to develop end user trust in the related technologies. Automated planning and scheduling systems often brings solutions to the users which are neither “obvious†nor immediately acceptable for them. This is due to the ability of these tools to take into account quite an amount of temporal and causal constraints and to employ resolution processes often designed to optimize the solution with respect to non trivial evaluation functions. To increase technology trust, the study of tools for verifying and validating plans and schedules produced by AI systems might be instrumental. In general, validation and verification techniques represent a needed complementary technology in developing domain independent architectures for automated problem solving. This paper presents a preliminary report of the issues concerned with the use of two software tools for formal verification of finite state systems to the validation of the solutions produced by MrSPOCK, a recent effort for building a timeline based planning tool in an ESA project. |
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yes |
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Sapienza @ mari @ Keps08 |
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25 |
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Della Penna, Giuseppe; Magazzeni, Daniele; Tofani, Alberto; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico |
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Title |
Automated Generation Of Optimal Controllers Through Model Checking Techniques |
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2008 |
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Informatics in Control Automation and Robotics. Selected Papers from ICINCO 2006 |
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107-119 |
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Springer |
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yes |
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Sapienza @ mari @ Dmtmt08 |
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26 |
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Della Penna, Giuseppe; Tofani, Alberto; Pecorari, Marcello; Raparelli, Orazio; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico |
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Title |
A Case Study on Automated Generation of Integration Tests |
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2006 |
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Fdl |
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278-284 |
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Ecsi |
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978-3-00-019710-9 |
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yes |
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Sapienza @ mari @ Dtprimt06 |
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27 |
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Bartolini, Novella; Tronci, Enrico |
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Title |
On Optimizing Service Availability of an Internet Based Architecture for Infrastructure Protection |
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2006 |
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Cnip |
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yes |
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Sapienza @ mari @ Bt06 |
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28 |
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Cecconi, Michele; Tronci, Enrico |
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Title |
Requirements Formalization and Validation for a Telecommunication Equipment Protection Switcher |
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2000 |
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Hase |
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IEEE Computer Society |
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0-7695-0927-4 |
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yes |
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Call Number |
Sapienza @ mari @ CeTro00 |
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29 |
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Author |
Tronci, Enrico |
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Title |
Introductory Paper |
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2006 |
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Sttt |
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8 |
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4-5 |
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355-358 |
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In today’s competitive market designing of digital systems (hardware as well as software) faces tremendous challenges. In fact, notwithstanding an ever decreasing project budget, time to market and product lifetime, designers are faced with an ever increasing system complexity and customer expected quality. The above situation calls for better and better formal verification techniques at all steps of the design flow. This special issue is devoted to publishing revised versions of contributions first presented at the 12th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME) held 21–24 October 2003 in L’Aquila, Italy. Authors of well regarded papers from CHARME’03 were invited to submit to this special issue. All papers included here have been suitably extended and have undergone an independent round of reviewing. |
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yes |
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Call Number |
Sapienza @ mari @ sttt06 |
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30 |
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Author |
Bobbio, Andrea; Ciancamerla, Ester; Minichino, Michele; Tronci, Enrico |
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Title |
Functional analysis of a telecontrol system and stochastic measures of its GSM/GPRS connections |
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2005 |
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Archives of Transport – International Journal of Transport Problems |
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17 |
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3-4 |
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Sapienza @ mari @ jtp05 |
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31 |
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Campagnano, Edoardo; Ciancamerla, Ester; Minichino, Michele; Tronci, Enrico |
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Title |
Automatic Analysis of a Safety Critical Tele Control System |
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2005 |
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24th International Conference on: Computer Safety, Reliability, and Security (SAFECOMP) |
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94-107 |
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We show how the Mur$\varphi$ model checker can be used to automatically carry out safety analysis of a quite complex hybrid system tele-controlling vehicles traffic inside a safety critical transport infrastructure such as a long bridge or a tunnel. We present the Mur$\varphi$ model we developed towards this end as well as the experimental results we obtained by running the Mur$\varphi$ verifier on our model. Our experimental results show that the approach presented here can be used to verify safety of critical dimensioning parameters (e.g. bandwidth) of the telecommunication network embedded in a safety critical system. |
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Springer |
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Fredrikstad, Norway |
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Winther, R.; Gran, B. A.; Dahll, G. |
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Lecture Notes in Computer Science |
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3688 |
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3-540-29200-4 |
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Call Number |
Sapienza @ mari @ safecomp05 |
Serial |
32 |
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