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	Author	Della Penna, Giuseppe; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico; Venturini Zilli, Marisa
	Title	Integrating RAM and Disk Based Verification within the Mur$\varphi$ Verifier			Type	Conference Article
	Year	2003	Publication	Correct Hardware Design and Verification Methods, 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings	Abbreviated Journal
	Volume		Issue		Pages	277-282
	Keywords
	Abstract	We present a verification algorithm that can automatically switch from RAM based verification to disk based verification without discarding the work done during the RAM based verification phase. This avoids having to choose beforehand the proper verification algorithm. Our experimental results show that typically our integrated algorithm is as fast as (sometime faster than) the fastest of the two base (i.e. RAM based and disk based) verification algorithms.
	Address
	Corporate Author				Thesis
	Publisher	Springer	Place of Publication		Editor	Geist, D.; Tronci, E.
	Language		Summary Language		Original Title
	Series Editor		Series Title	Lecture Notes in Computer Science	Abbreviated Series Title
	Series Volume	2860	Series Issue		Edition
	ISSN	3-540-20363-X	ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ DIMTZ03a			Serial	85
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	Author	Dipoppa, G.; D'Alessandro, G.; Semprini, R.; Tronci, E.
	Title	Integrating Automatic Verification of Safety Requirements in Railway Interlocking System Design			Type	Conference Article
	Year	2001	Publication	High Assurance Systems Engineering, 2001. Sixth IEEE International Symposium on	Abbreviated Journal
	Volume		Issue		Pages	209-219
	Keywords
	Abstract	A railway interlocking system (RIS) is an embedded system (namely a supervisory control system) that ensures the safe, operation of the devices in a railway station. RIS is a safety critical system. We explore the possibility of integrating automatic formal verification methods in a given industry RIS design flow. The main obstructions to be overcome in our work are: selecting a formal verification tool that is efficient enough to solve the verification problems at hand; and devising a cost effective integration strategy for such tool. We were able to devise a successful integration strategy meeting the above constraints without requiring major modification in the pre-existent design flow nor retraining of personnel. We run verification experiments for a RIS designed for the Singapore Subway. The experiments show that the RIS design flow obtained from our integration strategy is able to automatically verify real life RIS designs.
	Address
	Corporate Author				Thesis
	Publisher	IEEE Computer Society	Place of Publication	Albuquerque, NM, USA	Editor
	Language		Summary Language		Original Title
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	0-7695-1275-5	ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ hase01			Serial	45
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	Author	Tronci, Enrico
	Title	Hardware Verification, Boolean Logic Programming, Boolean Functional Programming			Type	Conference Article
	Year	1995	Publication	Tenth Annual IEEE Symposium on Logic in Computer Science (LICS)	Abbreviated Journal
	Volume		Issue		Pages	408-418
	Keywords
	Abstract	One of the main obstacles to automatic verification of finite state systems (FSSs) is state explosion. In this respect automatic verification of an FSS M using model checking and binary decision diagrams (BDDs) has an intrinsic limitation: no automatic global optimization of the verification task is possible until a BDD representation for M is generated. This is because systems and specifications are defined using different languages. To perform global optimization before generating a BDD representation for M we propose to use the same language to define systems and specifications. We show that first order logic on a Boolean domain yields an efficient functional programming language that can be used to represent, specify and automatically verify FSSs, e.g. on a SUN Sparc Station 2 we were able to automatically verify a 64 bit commercial multiplier.
	Address
	Corporate Author				Thesis
	Publisher	IEEE Computer Society	Place of Publication	San Diego, California	Editor
	Language		Summary Language		Original Title
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN		ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ lics95			Serial	56
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	Author	Bobbio, Andrea; Ciancamerla, Ester; Minichino, Michele; Tronci, Enrico
	Title	Functional analysis of a telecontrol system and stochastic measures of its GSM/GPRS connections			Type	Journal Article
	Year	2005	Publication	Archives of Transport – International Journal of Transport Problems	Abbreviated Journal
	Volume	17	Issue	3-4	Pages
	Keywords
	Abstract
	Address
	Corporate Author				Thesis
	Publisher		Place of Publication		Editor
	Language		Summary Language		Original Title
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN		ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ jtp05			Serial	31
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	Author	Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico
	Title	From Boolean Relations to Control Software			Type	Conference Article
	Year	2011	Publication	Proceedings of ICSEA 2011, The Sixth International Conference on Software Engineering Advances	Abbreviated Journal
	Volume		Issue		Pages	528-533
	Keywords
	Abstract	Many software as well digital hardware automatic synthesis methods define the set of implementations meeting the given system specifications with a boolean relation K. In such a context a fundamental step in the software (hardware) synthesis process is finding effective solutions to the functional equation defined by K. This entails finding a (set of) boolean function(s) F (typically represented using OBDDs, Ordered Binary Decision Diagrams) such that: 1) for all x for which K is satisfiable, K(x, F(x)) = 1 holds; 2) the implementation of F is efficient with respect to given implementation parameters such as code size or execution time. While this problem has been widely studied in digital hardware synthesis, little has been done in a software synthesis context. Unfortunately the approaches developed for hardware synthesis cannot be directly used in a software context. This motivates investigation of effective methods to solve the above problem when F has to be implemented with software. In this paper we present an algorithm that, from an OBDD representation for K, generates a C code implementation for F that has the same size as the OBDD for F and a WCET (Worst Case Execution Time) linear in nr, being n = \|x\| the number of input arguments for functions in F and r the number of functions in F.
	Address
	Corporate Author				Thesis
	Publisher	ThinkMind	Place of Publication		Editor
	Language		Summary Language		Original Title
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	978-1-61208-165-6	ISBN		Medium
	Area		Expedition		Conference
	Notes	Best Paper Award			Approved	yes
	Call Number	Sapienza @ mari @ icsea11			Serial	14
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	Author	Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico
	Title	From Boolean Functional Equations to Control Software			Type	Report
	Year	2011	Publication		Abbreviated Journal
	Volume	abs/1106.0468	Issue		Pages
	Keywords
	Abstract	Many software as well digital hardware automatic synthesis methods define the set of implementations meeting the given system specifications with a boolean relation K. In such a context a fundamental step in the software (hardware) synthesis process is finding effective solutions to the functional equation defined by K. This entails finding a (set of) boolean function(s) F (typically represented using OBDDs, Ordered Binary Decision Diagrams) such that: 1) for all x for which K is satisfiable, K(x, F(x)) = 1 holds; 2) the implementation of F is efficient with respect to given implementation parameters such as code size or execution time. While this problem has been widely studied in digital hardware synthesis, little has been done in a software synthesis context. Unfortunately the approaches developed for hardware synthesis cannot be directly used in a software context. This motivates investigation of effective methods to solve the above problem when F has to be implemented with software. In this paper we present an algorithm that, from an OBDD representation for K, generates a C code implementation for F that has the same size as the OBDD for F and a WCET (Worst Case Execution Time) at most O(nr), being n = \|x\| the number of arguments of functions in F and r the number of functions in F.
	Address
	Corporate Author				Thesis
	Publisher	CoRR, Technical Report	Place of Publication		Editor
	Language		Summary Language		Original Title
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN		ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @			Serial	105
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	Author	Tronci, Enrico
	Title	Formally Modeling a Metal Processing Plant and its Closed Loop Specifications			Type	Conference Article
	Year	1999	Publication	4th IEEE International Symposium on High-Assurance Systems Engineering (HASE)	Abbreviated Journal
	Volume		Issue		Pages	151
	Keywords
	Abstract	We present a case study on automatic synthesis of control software from formal specifications for an industrial automation control system. Our aim is to compare the effectiveness (i.e. design effort and controller quality) of automatic controller synthesis from closed loop formal specifications with that of manual controller design followed by automatic verification. The system to be controlled (plant) models a metal processing facility near Karlsruhe. We succeeded in automatically generating C code implementing a (correct by construction) embedded controller for such a plant from closed loop formal specifications. Our experimental results show that for industrial automation control systems automatic synthesis is a viable and profitable (especially as far as design effort is concerned) alternative to manual design followed by automatic verification.
	Address
	Corporate Author				Thesis
	Publisher	IEEE Computer Society	Place of Publication	Washington, D.C, USA	Editor
	Language		Summary Language		Original Title
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	0-7695-0418-3	ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ hase99			Serial	50
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	Author	Mazzini, Silvia; Puri, Stefano; Mari, Federico; Melatti, Igor; Tronci, Enrico
	Title	Formal Verification at System Level			Type	Conference Article
	Year	2009	Publication	In: DAta Systems In Aerospace (DASIA), Org. EuroSpace, Canadian Space Agency, CNES, ESA, EUMETSAT. Instanbul, Turkey, EuroSpace	Abbreviated Journal
	Volume		Issue		Pages
	Keywords
	Abstract	System Level Analysis calls for a language comprehensible to experts with different background and yet precise enough to support meaningful analyses. SysML is emerging as an effective balance between such conflicting goals. In this paper we outline some the results obtained as for SysML based system level functional formal verification by an ESA/ESTEC study, with a collaboration among INTECS and La Sapienza University of Roma. The study focuses on SysML based system level functional requirements techniques.
	Address
	Corporate Author				Thesis
	Publisher		Place of Publication		Editor
	Language		Summary Language		Original Title
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN		ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ Dasia09			Serial	20
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	Author	Focardi, Riccardo; Gorrieri, Roberto; Lanotte, Ruggero; Maggiolo-Schettini, Andrea; Martinelli, Fabio; Tini, Simone; Tronci, Enrico
	Title	Formal Models of Timing Attacks on Web Privacy			Type	Journal Article
	Year	2002	Publication	Electronic Notes in Theoretical Computer Science	Abbreviated Journal
	Volume	62	Issue		Pages	229-243
	Keywords
	Abstract	We model a timing attack on web privacy proposed by Felten and Schneider by using three different approaches: HL-Timed Automata, SMV model checker, and tSPA Process Algebra. Some comparative analysis on the three approaches is derived.
	Address
	Corporate Author				Thesis
	Publisher		Place of Publication		Editor
	Language		Summary Language		Original Title
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN		ISBN		Medium
	Area		Expedition		Conference
	Notes	TOSCA 2001, Theory of Concurrency, Higher Order Languages and Types			Approved	yes
	Call Number	Sapienza @ mari @ entcs02a			Serial	47
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	Author	Gribaudo, Marco; HorvÃ¡th, Andras; Bobbio, Andrea; Tronci, Enrico; Ciancamerla, Ester; Minichino, Michele
	Title	Fluid Petri Nets and hybrid model checking: a comparative case study			Type	Journal Article
	Year	2003	Publication	Int. Journal on: Reliability Engineering & System Safety	Abbreviated Journal
	Volume	81	Issue	3	Pages	239-257
	Keywords
	Abstract	The modeling and analysis of hybrid systems is a recent and challenging research area which is actually dominated by two main lines: a functional analysis based on the description of the system in terms of discrete state (hybrid) automata (whose goal is to ascertain conformity and reachability properties), and a stochastic analysis (whose aim is to provide performance and dependability measures). This paper investigates a unifying view between formal methods and stochastic methods by proposing an analysis methodology of hybrid systems based on Fluid Petri Nets (FPNs). FPNs can be analyzed directly using appropriate tools. Our paper shows that the same FPN model can be fed to different functional analyzers for model checking. In order to extensively explore the capability of the technique, we have converted the original FPN into languages for discrete as well as hybrid as well as stochastic model checkers. In this way, a first comparison among the modeling power of well known tools can be carried out. Our approach is illustrated by means of a Ã¢â‚¬â„¢real worldÃ¢â‚¬â„¢ hybrid system: the temperature control system of a co-generative plant.
	Address
	Corporate Author				Thesis
	Publisher	Elsevier	Place of Publication		Editor
	Language		Summary Language		Original Title
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN		ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ ress03			Serial	40
Permanent link to this record