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Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Title  |
Synthesis of Quantized Feedback Control Software for Discrete Time Linear Hybrid Systems |
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Conference Article |
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Year |
2010 |
Publication |
Computer Aided Verification |
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Volume |
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Pages |
180-195 |
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Abstract |
We present an algorithm that given a Discrete Time Linear Hybrid System returns a correct-by-construction software implementation K for a (near time optimal) robust quantized feedback controller for along with the set of states on which K is guaranteed to work correctly (controllable region). Furthermore, K has a Worst Case Execution Time linear in the number of bits of the quantization schema. |
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Springer Berlin / Heidelberg |
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Editor |
Touili, T.; Cook, B.; Jackson, P. |
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Lecture Notes in Computer Science |
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Series Volume |
6174 |
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Approved |
yes |
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Call Number |
Sapienza @ mari @ cav2010 |
Serial |
16 |
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Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Title |
Synthesizing Control Software from Boolean Relations |
Type |
Journal Article |
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Year |
2012 |
Publication |
International Journal on Advances in Software |
Abbreviated Journal |
Intern. Journal on Advances in SW |
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Volume |
vol. 5, nr 3&4 |
Issue |
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Pages |
212-223 |
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Keywords |
Control Software Synthesis; Embedded Systems; Model Checking |
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Abstract |
Many software as well digital hardware automatic
synthesis methods define the set of
implementations meeting the given system
specifications with a boolean relation K. In
such a context a fundamental step in the software
(hardware) synthesis process is finding effective
solutions to the functional equation defined by
K. This entails finding a (set of) boolean
function(s) F (typically represented using
OBDDs, Ordered Binary Decision Diagrams)
such that: 1) for all x for which K is
satisfiable, K(x, F(x)) = 1 holds; 2) the
implementation of F is efficient with respect
to given implementation parameters such as code
size or execution time. While this problem has
been widely studied in digital hardware synthesis,
little has been done in a software synthesis
context. Unfortunately, the approaches developed
for hardware synthesis cannot be directly used in
a software context. This motivates investigation
of effective methods to solve the above problem
when F has to be implemented with software. In
this paper, we present an algorithm that, from an
OBDD representation for K, generates a C code
implementation for F that has the same size as
the OBDD for F and a worst case execution time
linear in nr, being n = |x| the number of
input arguments for functions in F and r the
number of functions in F. Moreover, a formal
proof of the proposed algorithm correctness is
also shown. Finally, we present experimental
results showing effectiveness of the proposed
algorithm. |
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IARIA |
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Editor |
Luigi Lavazza |
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Edition |
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ISSN |
1942-2628 |
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yes |
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Call Number |
Sapienza @ melatti @ |
Serial |
108 |
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Author |
Mancini, Toni ; Mari, Federico ; Massini, Annalisa; Melatti, Igor; Tronci, Enrico |
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Title |
System Level Formal Verification via Distributed Multi-Core Hardware in the Loop Simulation |
Type |
Conference Article |
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Year |
2014 |
Publication |
Proc. of the 22nd Euromicro International Conference on Parallel, Distributed and Network-Based Processing |
Abbreviated Journal |
Euromicro International Conference on Parallel, Distributed and Network-Based Processing |
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IEEE Computer Society |
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no |
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Call Number |
Sapienza @ melatti @ |
Serial |
118 |
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Author |
Mancini, Toni; Mari, Federico; Massini, Annalisa; Melatti, Igor; Merli, Fabio; Tronci, Enrico |
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Title |
System Level Formal Verification via Model Checking Driven Simulation |
Type |
Conference Article |
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Year |
2013 |
Publication |
Proceedings of the 25th International Conference on Computer Aided Verification. July 13-19, 2013, Saint Petersburg, Russia |
Abbreviated Journal |
CAV 2013 |
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Issue |
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Pages |
296-312 |
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Springer - Verlag |
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Lecture Notes in Computer Science |
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Series Volume |
8044 |
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Edition |
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ISSN |
0302-9743 |
ISBN |
978-3-642-39798-1 |
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Approved |
yes |
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Call Number |
Sapienza @ mari @ |
Serial |
113 |
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Author |
Bucciarelli, Antonio; Salvo, Ivano |
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Title |
Totality, Definability and Boolean Circuits |
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Journal Article |
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Year |
1998 |
Publication |
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Volume |
1443 |
Issue |
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Pages |
808-819 |
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Abstract |
In the type frame originating from the flat domain of boolean values, we single out elements which are hereditarily total. We show that these elements can be defined, up to total equivalence, by sequential programs. The elements of an equivalence class of the totality equivalence relation (totality class) can be seen as different algorithms for computing a given set-theoretic boolean function. We show that the bottom element of a totality class, which is sequential, corresponds to the most eager algorithm, and the top to the laziest one. Finally we suggest a link between size of totality classes and a well known measure of complexity of boolean functions, namely their sensitivity. |
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Springer |
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Approved |
yes |
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Call Number |
Sapienza @ mari @ bucciarelli-salvo:98 |
Serial |
70 |
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Author |
Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Title |
Undecidability of Quantized State Feedback Control for Discrete Time Linear Hybrid Systems |
Type |
Book Chapter |
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Year |
2012 |
Publication |
Theoretical Aspects of Computing – ICTAC 2012 |
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Pages |
243-258 |
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Springer Berlin Heidelberg |
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Editor |
Roychoudhury, A.; D'Souza, M. |
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Lecture Notes in Computer Science |
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Series Volume |
7521 |
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ISBN |
978-3-642-32942-5 |
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Approved |
yes |
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Call Number |
Sapienza @ mari @ Mari2012 |
Serial |
99 |
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Author |
Mancini, T.; Mari, F.; Melatti, I.; Salvo, I.; Tronci, E.; Gruber, J.K.; Hayes, B.; Prodanovic, M.; Elmegaard, L. |
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Title |
User Flexibility Aware Price Policy Synthesis for Smart Grids |
Type |
Conference Article |
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Year |
2015 |
Publication |
Digital System Design (DSD), 2015 Euromicro Conference on |
Abbreviated Journal |
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Pages |
478-485 |
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Keywords |
Contracts; Current measurement; Load management; Power demand; Power measurement; State estimation; Substations; Grid State Estimation; Peak Shaving; Policy Robustness Verification; Price Policy Synthesis |
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Call Number |
Sapienza @ preissler @ Mancini_etal2015_3 |
Serial |
136 |
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Author |
Cesta, Amedeo; Finzi, Alberto; Fratini, Simone; Orlandini, Andrea; Tronci, Enrico |
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Title |
Validation and Verification Issues in a Timeline-based Planning System |
Type |
Conference Article |
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Year |
2008 |
Publication |
In E-Proc. of ICAPS Workshop on Knowledge Engineering for Planning and Scheduling |
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One of the key points to take into account to foster effective introduction of AI planning and scheduling systems in real world is to develop end user trust in the related technologies. Automated planning and scheduling systems often brings solutions to the users which are neither “obvious†nor immediately acceptable for them. This is due to the ability of these tools to take into account quite an amount of temporal and causal constraints and to employ resolution processes often designed to optimize the solution with respect to non trivial evaluation functions. To increase technology trust, the study of tools for verifying and validating plans and schedules produced by AI systems might be instrumental. In general, validation and verification techniques represent a needed complementary technology in developing domain independent architectures for automated problem solving. This paper presents a preliminary report of the issues concerned with the use of two software tools for formal verification of finite state systems to the validation of the solutions produced by MrSPOCK, a recent effort for building a timeline based planning tool in an ESA project. |
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yes |
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Call Number |
Sapienza @ mari @ Keps08 |
Serial |
25 |
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Author |
Cesta, Amedeo; Finzi, Alberto; Fratini, Simone; Orlandini, Andrea; Tronci, Enrico |
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Title |
Validation and verification issues in a timeline-based planning system |
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Journal Article |
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2010 |
Publication |
The Knowledge Engineering Review |
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Volume |
25 |
Issue |
03 |
Pages |
299-318 |
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Abstract |
One of the key points to take into account to foster effective introduction of AI planning and scheduling systems in real world is to develop end user trust in the related technologies. Automated planning and scheduling systems often brings solutions to the users which are neither “obvious†nor immediately acceptable for them. This is due to the ability of these tools to take into account quite an amount of temporal and causal constraints and to employ resolution processes often designed to optimize the solution with respect to non trivial evaluation functions. To increase technology trust, the study of tools for verifying and validating plans and schedules produced by AI systems might be instrumental. In general, validation and verification techniques represent a needed complementary technology in developing domain independent architectures for automated problem solving. This paper presents a preliminary report of the issues concerned with the use of two software tools for formal verification of finite state systems to the validation of the solutions produced by MrSPOCK, a recent effort for building a timeline based planning tool in an ESA project. |
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Cambridge University Press |
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yes |
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Call Number |
Sapienza @ mari @ Cffot10 |
Serial |
18 |
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Author |
Cesta, Amedeo; Finzi, Alberto; Fratini, Simone; Orlandini, Andrea; Tronci, Enrico |
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Title |
Verifying Flexible Timeline-based Plans |
Type |
Conference Article |
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Year |
2009 |
Publication |
E-Proc. of ICAPS Workshop on Validation and Verification of Planning and Scheduling Systems |
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The synthesis of flexible temporal plans has demonstrated wide applications possibilities in heterogeneous domains. We are currently studying the connection between plan generation and execution from the particular perspective of verifying a flexible plan before actual execution. This paper explores how a model-checking verification tool, based on UPPAAL-TIGA, is suitable for verifying flexible temporal plans. We first describe the formal model, the formalism, and the verification method. Furthermore we discuss our own approach and some preliminary empirical results using a real-world case study. |
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yes |
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Call Number |
Sapienza @ mari @ Vvps09 |
Serial |
23 |
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