| Records |
| Author |
Tronci, Enrico |
| Title |
Equational Programming in Lambda-Calculus via SL-Systems. Part 2 |
Type |
Journal Article |
| Year |
1996 |
Publication |
Theoretical Computer Science |
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160 |
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1&2 |
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185-216 |
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yes |
| Call Number |
Sapienza @ mari @ tcs96a |
Serial |
55 |
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| Author |
Tronci, Enrico |
| Title |
Equational Programming in Lambda-Calculus via SL-Systems. Part 1 |
Type |
Journal Article |
| Year |
1996 |
Publication |
Theoretical Computer Science |
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| Volume |
160 |
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1&2 |
Pages |
145-184 |
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yes |
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Sapienza @ mari @ tcs96 |
Serial |
54 |
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| Author |
Gorrieri, Roberto; Lanotte, Ruggero; Maggiolo-Schettini, Andrea; Martinelli, Fabio; Tini, Simone; Tronci, Enrico |
| Title |
Automated analysis of timed security: a case study on web privacy |
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Journal Article |
| Year |
2004 |
Publication |
International Journal of Information Security |
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| Volume |
2 |
Issue |
3-4 |
Pages |
168-186 |
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This paper presents a case study on an automated analysis of real-time security models. The case study on a web system (originally proposed by Felten and Schneider) is presented that shows a timing attack on the privacy of browser users. Three different approaches are followed: LH-Timed Automata (analyzed using the model checker HyTech), finite-state automata (analyzed using the model checker NuSMV), and process algebras (analyzed using the model checker CWB-NC). A comparative analysis of these three approaches is given. |
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yes |
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Sapienza @ mari @ ijis04 |
Serial |
33 |
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| Author |
Della Penna, Giuseppe; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico; Venturini Zilli, Marisa |
| Title |
Finite horizon analysis of Markov Chains with the Mur$\varphi$ verifier |
Type |
Journal Article |
| Year |
2006 |
Publication |
Int. J. Softw. Tools Technol. Transf. |
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| Volume |
8 |
Issue |
4 |
Pages |
397-409 |
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In this paper we present an explicit disk-based verification algorithm for Probabilistic Systems defining discrete time/finite state Markov Chains. Given a Markov Chain and an integer k (horizon), our algorithm checks whether the probability of reaching an error state in at most k steps is below a given threshold. We present an implementation of our algorithm within a suitable extension of the Mur$\varphi$ verifier. We call the resulting probabilistic model checker FHP-Mur$\varphi$ (Finite Horizon Probabilistic Mur$\varphi$). We present experimental results comparing FHP-Mur$\varphi$ with (a finite horizon subset of) PRISM, a state-of-the-art symbolic model checker for Markov Chains. Our experimental results show that FHP-Mur$\varphi$ can handle systems that are out of reach for PRISM, namely those involving arithmetic operations on the state variables (e.g. hybrid systems). |
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Springer-Verlag |
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Berlin, Heidelberg |
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1433-2779 |
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yes |
| Call Number |
Sapienza @ mari @ Dimtz06 |
Serial |
78 |
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| Author |
Tronci, Enrico |
| Title |
Introductory Paper |
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Journal Article |
| Year |
2006 |
Publication |
Sttt |
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| Volume |
8 |
Issue |
4-5 |
Pages |
355-358 |
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In today’s competitive market designing of digital systems (hardware as well as software) faces tremendous challenges. In fact, notwithstanding an ever decreasing project budget, time to market and product lifetime, designers are faced with an ever increasing system complexity and customer expected quality. The above situation calls for better and better formal verification techniques at all steps of the design flow. This special issue is devoted to publishing revised versions of contributions first presented at the 12th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME) held 21–24 October 2003 in L’Aquila, Italy. Authors of well regarded papers from CHARME’03 were invited to submit to this special issue. All papers included here have been suitably extended and have undergone an independent round of reviewing. |
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yes |
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Sapienza @ mari @ sttt06 |
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30 |
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| Author |
Della Penna, Giuseppe; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico; Venturini Zilli, Marisa |
| Title |
Exploiting Transition Locality in Automatic Verification of Finite State Concurrent Systems |
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Journal Article |
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2004 |
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Sttt |
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| Volume |
6 |
Issue |
4 |
Pages |
320-341 |
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In this paper we show that statistical properties of the transition graph of a system to be verified can be exploited to improve memory or time performances of verification algorithms. We show experimentally that protocols exhibit transition locality. That is, with respect to levels of a breadth-first state space exploration, state transitions tend to be between states belonging to close levels of the transition graph. We support our claim by measuring transition locality for the set of protocols included in the Mur$\varphi$ verifier distribution. We present a cache-based verification algorithm that exploits transition locality to decrease memory usage and a disk-based verification algorithm that exploits transition locality to decrease disk read accesses, thus reducing the time overhead due to disk usage. Both algorithms have been implemented within the Mur$\varphi$ verifier. Our experimental results show that our cache-based algorithm can typically save more than 40% of memory with an average time penalty of about 50% when using (Mur$\varphi$) bit compression and 100% when using bit compression and hash compaction, whereas our disk-based verification algorithm is typically more than ten times faster than a previously proposed disk-based verification algorithm and, even when using 10% of the memory needed to complete verification, it is only between 40 and 530% (300% on average) slower than (RAM) Mur$\varphi$ with enough memory to complete the verification task at hand. Using just 300 MB of memory our disk-based Mur$\varphi$ was able to complete verification of a protocol with about $10^9$ reachable states. This would require more than 5 GB of memory using standard Mur$\varphi$. |
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yes |
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Sapienza @ mari @ DIMTZ04j |
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91 |
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| Author |
Bucciarelli, Antonio; Salvo, Ivano |
| Title |
Totality, Definability and Boolean Circuits |
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Journal Article |
| Year |
1998 |
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| Volume |
1443 |
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808-819 |
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In the type frame originating from the flat domain of boolean values, we single out elements which are hereditarily total. We show that these elements can be defined, up to total equivalence, by sequential programs. The elements of an equivalence class of the totality equivalence relation (totality class) can be seen as different algorithms for computing a given set-theoretic boolean function. We show that the bottom element of a totality class, which is sequential, corresponds to the most eager algorithm, and the top to the laziest one. Finally we suggest a link between size of totality classes and a well known measure of complexity of boolean functions, namely their sensitivity. |
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Springer |
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yes |
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Sapienza @ mari @ bucciarelli-salvo:98 |
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70 |
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| Author |
Lanotte, Ruggero; Maggiolo-Schettini, Andrea; Tini, Simone; Troina, Angelo; Tronci, Enrico |
| Title |
Automatic Covert Channel Analysis of a Multilevel Secure Component |
Type |
Conference Article |
| Year |
2004 |
Publication |
Information and Communications Security, 6th International Conference, ICICS 2004, Malaga, Spain, October 27-29, 2004, Proceedings |
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249-261 |
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The NRL Pump protocol defines a multilevel secure component whose goal is to minimize leaks of information from high level systems to lower level systems, without degrading average time performances. We define a probabilistic model for the NRL Pump and show how a probabilistic model checker (FHP-mur$\varphi$) can be used to estimate the capacity of a probabilistic covert channel in the NRL Pump. We are able to compute the probability of a security violation as a function of time for various configurations of the system parameters (e.g. buffer sizes, moving average size, etc). Because of the model complexity, our results cannot be obtained using an analytical approach and, because of the low probabilities involved, it can be hard to obtain them using a simulator. |
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Springer |
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Lopez, J.; Qing, S.; Okamoto, E. |
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Lecture Notes in Computer Science |
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3269 |
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yes |
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Sapienza @ mari @ icics04 |
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34 |
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| Author |
Della Penna, Giuseppe; Magazzeni, Daniele; Tofani, Alberto; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico |
| Title |
Automated Generation Of Optimal Controllers Through Model Checking Techniques |
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Book Chapter |
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2008 |
Publication |
Informatics in Control Automation and Robotics. Selected Papers from ICINCO 2006 |
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107-119 |
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Springer |
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yes |
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Sapienza @ mari @ Dmtmt08 |
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26 |
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| Author |
Mari, Federico; Tronci, Enrico |
| Title |
CEGAR Based Bounded Model Checking of Discrete Time Hybrid Systems |
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Conference Article |
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2007 |
Publication |
Hybrid Systems: Computation and Control (HSCC 2007) |
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399-412 |
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Model Checking, Abstraction, CEGAR, SAT, Hybrid Systems, DTHS |
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Many hybrid systems can be conveniently modeled as Piecewise Affine Discrete Time Hybrid Systems PA-DTHS. As well known Bounded Model Checking (BMC) for such systems comes down to solve a Mixed Integer Linear Programming (MILP) feasibility problem. We present a SAT based BMC algorithm for automatic verification of PA-DTHSs. Using Counterexample Guided Abstraction Refinement (CEGAR) our algorithm gradually transforms a PA-DTHS verification problem into larger and larger SAT problems. Our experimental results show that our approach can handle PA-DTHSs that are more then 50 times larger than those that can be handled using a MILP solver. |
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Springer |
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Bemporad, A.; Bicchi, A.; Buttazzo, G.C. |
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Lecture Notes in Computer Science |
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4416 |
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yes |
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Sapienza @ mari @ MarTro07 |
Serial |
92 |
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