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	Author	Gribaudo, Marco; HorvÃ¡th, Andras; Bobbio, Andrea; Tronci, Enrico; Ciancamerla, Ester; Minichino, Michele
	Title	Model-Checking Based on Fluid Petri Nets for the Temperature Control System of the ICARO Co-generative Plant			Type	Conference Article
	Year	2002	Publication	21st International Conference on Computer Safety, Reliability and Security (SAFECOMP)	Abbreviated Journal
	Volume		Issue		Pages	273-283
	Keywords
	Abstract	The modeling and analysis of hybrid systems is a recent and challenging research area which is actually dominated by two main lines: a functional analysis based on the description of the system in terms of discrete state (hybrid) automata (whose goal is to ascertain for conformity and reachability properties), and a stochastic analysis (whose aim is to provide performance and dependability measures). This paper investigates a unifying view between formal methods and stochastic methods by proposing an analysis methodology of hybrid systems based on Fluid Petri Nets (FPN). It is shown that the same FPN model can be fed to a functional analyser for model checking as well as to a stochastic analyser for performance evaluation. We illustrate our approach and show its usefulness by applying it to a Ã¢â‚¬Å“real worldÃ¢â‚¬Â hybrid system: the temperature control system of a co-generative plant.
	Address
	Corporate Author				Thesis
	Publisher	Springer	Place of Publication	Catania, Italy	Editor	Anderson, S.; Bologna, S.; Felici, M.
	Language		Summary Language		Original Title
	Series Editor		Series Title	Lecture Notes in Computer Science	Abbreviated Series Title
	Series Volume	2434	Series Issue		Edition
	ISSN	3-540-44157-3	ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ safecomp02			Serial	42
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	Author	Tronci, Enrico; Della Penna, Giuseppe; Intrigila, Benedetto; Venturini Zilli, Marisa
	Title	A Probabilistic Approach to Automatic Verification of Concurrent Systems			Type	Conference Article
	Year	2001	Publication	8th Asia-Pacific Software Engineering Conference (APSEC)	Abbreviated Journal
	Volume		Issue		Pages	317-324
	Keywords
	Abstract	The main barrier to automatic verification of concurrent systems is the huge amount of memory required to complete the verification task (state explosion). In this paper we present a probabilistic algorithm for automatic verification via model checking. Our algorithm trades space with time. In particular, when memory is full because of state explosion our algorithm does not give up verification. Instead it just proceeds at a lower speed and its results will only hold with some arbitrarily small error probability. Our preliminary experimental results show that by using our probabilistic algorithm we can typically save more than 30% of RAM with an average time penalty of about 100% w.r.t. a deterministic state space exploration with enough memory to complete the verification task. This is better than giving up the verification task because of lack of memory.
	Address
	Corporate Author				Thesis
	Publisher	IEEE Computer Society	Place of Publication	Macau, China	Editor
	Language		Summary Language		Original Title
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	0-7695-1408-1	ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ apsec01			Serial	43
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	Author	Tronci, Enrico; Della Penna, Giuseppe; Intrigila, Benedetto; Venturini Zilli, Marisa
	Title	Exploiting Transition Locality in Automatic Verification			Type	Conference Article
	Year	2001	Publication	11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME)	Abbreviated Journal
	Volume		Issue		Pages	259-274
	Keywords
	Abstract	In this paper we present an algorithm to contrast state explosion when using Explicit State Space Exploration to verify protocols. We show experimentally that protocols exhibit transition locality. We present a verification algorithm that exploits transition locality as well as an implementation of it within the Mur$\varphi$ verifier. Our algorithm is compatible with all Breadth First (BF) optimization techniques present in the Mur$\varphi$ verifier and it is by no means a substitute for any of them. In fact, since our algorithm trades space with time, it is typically most useful when one runs out of memory and has already used all other state reduction techniques present in the Mur$\varphi$ verifier. Our experimental results show that using our approach we can typically save more than 40% of RAM with an average time penalty of about 50% when using (Mur$\varphi$) bit compression and 100% when using bit compression and hash compaction.
	Address
	Corporate Author				Thesis
	Publisher	Springer	Place of Publication	Livingston, Scotland, UK	Editor	Margaria, T.; Melham, T.F.
	Language		Summary Language		Original Title
	Series Editor		Series Title	Lecture Notes in Computer Science	Abbreviated Series Title
	Series Volume	2144	Series Issue		Edition
	ISSN	3-540-42541-1	ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ charme01			Serial	44
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	Author	Dipoppa, G.; D'Alessandro, G.; Semprini, R.; Tronci, E.
	Title	Integrating Automatic Verification of Safety Requirements in Railway Interlocking System Design			Type	Conference Article
	Year	2001	Publication	High Assurance Systems Engineering, 2001. Sixth IEEE International Symposium on	Abbreviated Journal
	Volume		Issue		Pages	209-219
	Keywords
	Abstract	A railway interlocking system (RIS) is an embedded system (namely a supervisory control system) that ensures the safe, operation of the devices in a railway station. RIS is a safety critical system. We explore the possibility of integrating automatic formal verification methods in a given industry RIS design flow. The main obstructions to be overcome in our work are: selecting a formal verification tool that is efficient enough to solve the verification problems at hand; and devising a cost effective integration strategy for such tool. We were able to devise a successful integration strategy meeting the above constraints without requiring major modification in the pre-existent design flow nor retraining of personnel. We run verification experiments for a RIS designed for the Singapore Subway. The experiments show that the RIS design flow obtained from our integration strategy is able to automatically verify real life RIS designs.
	Address
	Corporate Author				Thesis
	Publisher	IEEE Computer Society	Place of Publication	Albuquerque, NM, USA	Editor
	Language		Summary Language		Original Title
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	0-7695-1275-5	ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ hase01			Serial	45
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	Author	Tronci, Enrico
	Title	Automatic Synthesis of Control Software for an Industrial Automation Control System			Type	Conference Article
	Year	1999	Publication	Proc.of: 14th IEEE International Conference on: Automated Software Engineering (ASE)	Abbreviated Journal
	Volume		Issue		Pages	247-250
	Keywords
	Abstract	We present a case study on automatic synthesis of control software from formal specifications for an industrial automation control system. Our aim is to compare the effectiveness (i.e. design effort and controller quality) of automatic controller synthesis from closed loop formal specifications with that of manual controller design, followed by automatic verification. Our experimental results show that for industrial automation control systems, automatic synthesis is a viable and profitable (especially as far as design effort is concerned) alternative to manual design, followed by automatic verification.
	Address
	Corporate Author				Thesis
	Publisher		Place of Publication	Cocoa Beach, Florida, USA	Editor
	Language		Summary Language		Original Title
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN		ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ ase99			Serial	49
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	Author	Tronci, Enrico
	Title	Formally Modeling a Metal Processing Plant and its Closed Loop Specifications			Type	Conference Article
	Year	1999	Publication	4th IEEE International Symposium on High-Assurance Systems Engineering (HASE)	Abbreviated Journal
	Volume		Issue		Pages	151
	Keywords
	Abstract	We present a case study on automatic synthesis of control software from formal specifications for an industrial automation control system. Our aim is to compare the effectiveness (i.e. design effort and controller quality) of automatic controller synthesis from closed loop formal specifications with that of manual controller design followed by automatic verification. The system to be controlled (plant) models a metal processing facility near Karlsruhe. We succeeded in automatically generating C code implementing a (correct by construction) embedded controller for such a plant from closed loop formal specifications. Our experimental results show that for industrial automation control systems automatic synthesis is a viable and profitable (especially as far as design effort is concerned) alternative to manual design followed by automatic verification.
	Address
	Corporate Author				Thesis
	Publisher	IEEE Computer Society	Place of Publication	Washington, D.C, USA	Editor
	Language		Summary Language		Original Title
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	0-7695-0418-3	ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ hase99			Serial	50
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	Author	Fantechi, Alessandro; Gnesi, Stefania; Mazzanti, Franco; Pugliese, Rosario; Tronci, Enrico
	Title	A Symbolic Model Checker for ACTL			Type	Conference Article
	Year	1998	Publication	International Workshop on Current Trends in Applied Formal Method (FM-Trends)	Abbreviated Journal
	Volume		Issue		Pages	228-242
	Keywords
	Abstract	We present SAM, a symbolic model checker for ACTL, the action-based version of CTL. SAM relies on implicit representations of Labeled Transition Systems (LTSs), the semantic domain for ACTL formulae, and uses symbolic manipulation algorithms. SAM has been realized by translating (networks of) LTSs and, possibly recursive, ACTL formulae into BSP (Boolean Symbolic Programming), a programming language aiming at defining computations on boolean functions, and by using the BSP interpreter to carry out computations (i.e. verifications).
	Address
	Corporate Author				Thesis
	Publisher	Springer	Place of Publication	Boppard, Germany	Editor	Hutter, D.; Stephan, W.; Traverso, P.; Ullmann, M.
	Language		Summary Language		Original Title
	Series Editor		Series Title	Lecture Notes in Computer Science	Abbreviated Series Title
	Series Volume	1641	Series Issue		Edition
	ISSN	3-540-66462-9	ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ fm-trends98			Serial	51
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	Author	Tronci, Enrico
	Title	Automatic Synthesis of Controllers from Formal Specifications			Type	Conference Article
	Year	1998	Publication	Proc of 2nd IEEE International Conference on Formal Engineering Methods (ICFEM)	Abbreviated Journal
	Volume		Issue		Pages	134-143
	Keywords
	Abstract	Many safety critical reactive systems are indeed embedded control systems. Usually a control system can be partitioned into two main subsystems: a controller and a plant. Roughly speaking: the controller observes the state of the plant and sends commands (stimulus) to the plant to achieve predefined goals. We show that when the plant can be modeled as a deterministic finite state system (FSS) it is possible to effectively use formal methods to automatically synthesize the program implementing the controller from the plant model and the given formal specifications for the closed loop system (plant+controller). This guarantees that the controller program is correct by construction. To the best of our knowledge there is no previously published effective algorithm to extract executable code for the controller from closed loop formal specifications. We show practical usefulness of our techniques by giving experimental results on their use to synthesize C programs implementing optimal controllers (OCs) for plants with more than 109 states.
	Address
	Corporate Author				Thesis
	Publisher		Place of Publication	Brisbane, Queensland, Australia	Editor
	Language		Summary Language		Original Title
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN		ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ icfem98			Serial	52
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	Author	Pugliese, Rosario; Tronci, Enrico
	Title	Automatic Verification of a Hydroelectric Power Plant			Type	Conference Article
	Year	1996	Publication	Third International Symposium of Formal Methods Europe (FME), Co-Sponsored by IFIP WG 14.3	Abbreviated Journal
	Volume		Issue		Pages	425-444
	Keywords
	Abstract	We analyze the specification of a hydroelectric power plant by ENEL (the Italian Electric Company). Our goal is to show that for the specification of the plant (its control system in particular) some given properties hold. We were provided with an informal specification of the plant. From such informal specification we wrote a formal specification using the CCS/Meije process algebra formalism. We defined properties using μ-calculus. Automatic verification was carried out using model checking. This was done by translating our process algebra definitions (the model) and μ-calculus formulas into BDDs. In this paper we present the informal specification of the plant, its formal specification, some of the properties we verified and experimental results.
	Address
	Corporate Author				Thesis
	Publisher	Springer	Place of Publication	Oxford, UK	Editor	Gaudel, M.-C.; Woodcock, J.
	Language		Summary Language		Original Title
	Series Editor		Series Title	Lecture Notes in Computer Science	Abbreviated Series Title
	Series Volume	1051	Series Issue		Edition
	ISSN	3-540-60973-3	ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ fme96			Serial	53
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	Author	Tronci, Enrico
	Title	Hardware Verification, Boolean Logic Programming, Boolean Functional Programming			Type	Conference Article
	Year	1995	Publication	Tenth Annual IEEE Symposium on Logic in Computer Science (LICS)	Abbreviated Journal
	Volume		Issue		Pages	408-418
	Keywords
	Abstract	One of the main obstacles to automatic verification of finite state systems (FSSs) is state explosion. In this respect automatic verification of an FSS M using model checking and binary decision diagrams (BDDs) has an intrinsic limitation: no automatic global optimization of the verification task is possible until a BDD representation for M is generated. This is because systems and specifications are defined using different languages. To perform global optimization before generating a BDD representation for M we propose to use the same language to define systems and specifications. We show that first order logic on a Boolean domain yields an efficient functional programming language that can be used to represent, specify and automatically verify FSSs, e.g. on a SUN Sparc Station 2 we were able to automatically verify a 64 bit commercial multiplier.
	Address
	Corporate Author				Thesis
	Publisher	IEEE Computer Society	Place of Publication	San Diego, California	Editor
	Language		Summary Language		Original Title
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN		ISBN		Medium
	Area		Expedition		Conference
	Notes				Approved	yes
	Call Number	Sapienza @ mari @ lics95			Serial	56
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