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Mancini, T. ; Mari, F.; Massini, A.; Melatti, I.; Salvo, I.; Tronci, E. |
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Title |
On minimising the maximum expected verification time |
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Journal Article |
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2017 |
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Information Processing Letters |
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Sapienza @ mari @ |
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163 |
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Author |
Mancini, T.; Mari, F.; Massini, A.; Melatti, I.; Tronci, E. |
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Title |
On Checking Equivalence of Simulation Scripts |
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Journal Article |
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2021 |
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Journal of Logical and Algebraic Methods in Programming |
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100640 |
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Formal verification, Simulation based formal verification, Formal Verification of cyber-physical systems, System-level formal verification |
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To support Model Based Design of Cyber-Physical Systems (CPSs) many simulation based approaches to System Level Formal Verification (SLFV) have been devised. Basically, these are Bounded Model Checking approaches (since simulation horizon is of course bounded) relying on simulators to compute the system dynamics and thereby verify the given system properties. The main obstacle to simulation based SLFV is the large number of simulation scenarios to be considered and thus the huge amount of simulation time needed to complete the verification task. To save on computation time, simulation based SLFV approaches exploit the capability of simulators to save and restore simulation states. Essentially, such a time saving is obtained by optimising the simulation script defining the simulation activity needed to carry out the verification task. Although such approaches aim to (bounded) formal verification, as a matter of fact, the proof of correctness of the methods to optimise simulation scripts basically relies on an intuitive semantics for simulation scripting languages. This hampers the possibility of formally showing that the optimisations introduced to speed up the simulation activity do not actually omit checking of relevant behaviours for the system under verification. The aim of this paper is to fill the above gap by presenting an operational semantics for simulation scripting languages and by proving soundness and completeness properties for it. This, in turn, enables formal proofs of equivalence between unoptimised and optimised simulation scripts. |
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2352-2208 |
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MCLab @ davi @ Mancini2021100640 |
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183 |
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Author |
Mancini, T.; Mari, F.; Massini, A.; Melatti, I.; Tronci, E. |
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Title |
Anytime system level verification via parallel random exhaustive hardware in the loop simulation |
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Journal Article |
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2016 |
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Microprocessors and Microsystems |
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41 |
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12-28 |
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Model Checking of Hybrid Systems; Model checking driven simulation; Hardware in the loop simulation |
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Abstract System level verification of cyber-physical systems has the goal of verifying that the whole (i.e., software + hardware) system meets the given specifications. Model checkers for hybrid systems cannot handle system level verification of actual systems. Thus, Hardware In the Loop Simulation (HILS) is currently the main workhorse for system level verification. By using model checking driven exhaustive HILS, System Level Formal Verification (SLFV) can be effectively carried out for actual systems. We present a parallel random exhaustive HILS based model checker for hybrid systems that, by simulating all operational scenarios exactly once in a uniform random order, is able to provide, at any time during the verification process, an upper bound to the probability that the System Under Verification exhibits an error in a yet-to-be-simulated scenario (Omission Probability). We show effectiveness of the proposed approach by presenting experimental results on SLFV of the Inverted Pendulum on a Cart and the Fuel Control System examples in the Simulink distribution. To the best of our knowledge, no previously published model checker can exhaustively verify hybrid systems of such a size and provide at any time an upper bound to the Omission Probability. |
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0141-9331 |
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MCLab @ davi @ Mancini201612 |
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155 |
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Author |
Brizzolari, Francesco; Melatti, Igor; Tronci, Enrico; Della Penna, Giuseppe |
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Title |
Disk Based Software Verification via Bounded Model Checking |
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Conference Article |
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2007 |
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APSEC '07: Proceedings of the 14th Asia-Pacific Software Engineering Conference |
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358-365 |
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One of the most successful approach to automatic software verification is SAT based bounded model checking (BMC). One of the main factors limiting the size of programs that can be automatically verified via BMC is the huge number of clauses that the backend SAT solver has to process. In fact, because of this, the SAT solver may easily run out of RAM. We present two disk based algorithms that can considerably decrease the number of clauses that a BMC backend SAT solver has to process in RAM. Our experimental results show that using our disk based algorithms we can automatically verify programs that are out of reach for RAM based BMC. |
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IEEE Computer Society |
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Washington, DC, USA |
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0-7695-3057-5 |
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yes |
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Sapienza @ mari @ Bmtd07 |
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76 |
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Author |
Alimguzhin, Vadim; Mari, Federico; Melatti, Igor; Salvo, Ivano; Tronci, Enrico |
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Automatic Control Software Synthesis for Quantized Discrete Time Hybrid Systems |
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Conference Article |
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2012 |
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Proceedings of the 51th IEEE Conference on Decision and Control, CDC 2012, December 10-13, 2012, Maui, HI, USA |
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6120-6125 |
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IEEE |
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978-1-4673-2065-8 |
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Techreport version can be found at http://arxiv.org/abs/1207.4098 |
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yes |
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Sapienza @ mari @ cdc12 |
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96 |
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Intrigila, Benedetto; Magazzeni, Daniele; Melatti, Igor; Tronci, Enrico |
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A Model Checking Technique for the Verification of Fuzzy Control Systems |
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Conference Article |
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2005 |
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CIMCA '05: Proceedings of the International Conference on Computational Intelligence for Modelling, Control and Automation and International Conference on Intelligent Agents, Web Technologies and Internet Commerce Vol-1 (CIMCA-IAWTIC'06) |
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536-542 |
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Fuzzy control is well known as a powerful technique for designing and realizing control systems. However, statistical evidence for their correct behavior may be not enough, even when it is based on a large number of samplings. In order to provide a more systematic verification process, the cell-to-cell mapping technology has been used in a number of cases as a verification tool for fuzzy control systems and, more recently, to assess their optimality and robustness. However, cell-to-cell mapping is typically limited in the number of cells it can explore. To overcome this limitation, in this paper we show how model checking techniques may be instead used to verify the correct behavior of a fuzzy control system. To this end, we use a modified version of theMurphi verifier, which ease the modeling phase by allowing to use finite precision real numbers and external C functions. In this way, also already designed simulators may be used for the verification phase. With respect to the cell mapping technique, our approach appears to be complementary; indeed, it explores a much larger number of states, at the cost of being less informative on the global dynamic of the system. |
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IEEE Computer Society |
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Washington, DC, USA |
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0-7695-2504-0-01 |
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yes |
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Sapienza @ mari @ Immt05 |
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75 |
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Della Penna, Giuseppe; Magazzeni, Daniele; Tofani, Alberto; Intrigila, Benedetto; Melatti, Igor; Tronci, Enrico |
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Automatic Synthesis of Robust Numerical Controllers |
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2007 |
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Icas '07 |
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4 |
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A major problem of numerical controllers is their robustness, i.e. the state read from the plant may not be in the controller table, although it may be close to some states in the table. For continuous systems, this problem is typically handled by interpolation techniques. Unfortunately, when the plant contains both continuous and discrete variables, the interpolation approach does not work well. To cope with this kind of systems, we propose a general methodology that exploits explicit model checking in an innovative way to automatically synthesize a (time-) optimal numerical controller from a plant specification and apply an optimized strengthening algorithm only on the most significant states, in order to reach an acceptable robustness degree. We implemented all the algorithms within our CGMurphi tool, an extension of the well-known CMurphi verifier, and tested the effectiveness of our approach by applying it to the well-known truck and trailer obstacles avoidance problem. |
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IEEE Computer Society |
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0-7695-2859-5 |
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yes |
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Sapienza @ mari @ Dmtimt07 |
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89 |
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Bobbio, Andrea; Ciancamerla, Ester; Di Blasi, Saverio; Iacomini, Alessandro; Mari, Federico; Melatti, Igor; Minichino, Michele; Scarlatti, Alessandro; Tronci, Enrico; Terruggia, Roberta; Zendri, Emilio |
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Risk analysis via heterogeneous models of SCADA interconnecting Power Grids and Telco networks |
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2009 |
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Proceedings of Fourth International Conference on Risks and Security of Internet and Systems (CRiSIS) |
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90-97 |
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The automation of power grids by means of supervisory control and data acquisition (SCADA) systems has led to an improvement of power grid operations and functionalities but also to pervasive cyber interdependencies between power grids and telecommunication networks. Many power grid services are increasingly depending upon the adequate functionality of SCADA system which in turn strictly depends on the adequate functionality of its communication infrastructure. We propose to tackle the SCADA risk analysis by means of different and heterogeneous modeling techniques and software tools. We demonstrate the applicability of our approach through a case study on an actual SCADA system for an electrical power distribution grid. The modeling techniques we discuss aim at providing a probabilistic dependability analysis, followed by a worst case analysis in presence of malicious attacks and a real-time performance evaluation. |
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Fourth International Conference on Risks and Security of Internet and Systems (CRiSIS) |
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yes |
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Sapienza @ mari @ crisis09 |
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17 |
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Mancini, Toni; Mari, Federico; Massini, Annalisa; Melatti, Igor; Tronci, Enrico |
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Title |
Anytime System Level Verification via Random Exhaustive Hardware In The Loop Simulation |
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Conference Article |
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2014 |
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In Proceedings of 17th EuroMicro Conference on Digital System Design (DSD 2014) |
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MCLab @ davi @ |
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122 |
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Alimguzhin, V.; Mari, F.; Melatti, I.; Tronci, E.; Ebeid, E.; Mikkelsen, S.A.; Jacobsen, R.H.; Gruber, J.K.; Hayes, B.; Huerta, F.; Prodanovic, M. |
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A Glimpse of SmartHG Project Test-bed and Communication Infrastructure |
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2015 |
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Digital System Design (DSD), 2015 Euromicro Conference on |
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225-232 |
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Batteries; Control systems; Databases; Production; Sensors; Servers; Smart grids; Grid State Estimation; Peak Shaving; Policy Robustness Verification; Price Policy Synthesis |
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Sapienza @ preissler @ Alimguzhin_etal2015 |
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127 |
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